From patchwork Wed Jul 1 15:28:10 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michel Thierry X-Patchwork-Id: 6704321 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 49EE89F38C for ; Wed, 1 Jul 2015 15:28:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A7243204F6 for ; Wed, 1 Jul 2015 15:28:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id BE0C320501 for ; Wed, 1 Jul 2015 15:28:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 235877A083; Wed, 1 Jul 2015 08:28:15 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 6ED8D7A086; Wed, 1 Jul 2015 08:28:14 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 01 Jul 2015 08:28:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,386,1432623600"; d="scan'208";a="738570343" Received: from michelth-linux2.isw.intel.com ([10.102.226.189]) by fmsmga001.fm.intel.com with ESMTP; 01 Jul 2015 08:28:13 -0700 From: Michel Thierry To: intel-gfx@lists.freedesktop.org Date: Wed, 1 Jul 2015 16:28:10 +0100 Message-Id: <1435764490-12029-3-git-send-email-michel.thierry@intel.com> X-Mailer: git-send-email 2.4.5 In-Reply-To: <1435764490-12029-1-git-send-email-michel.thierry@intel.com> References: <1435062089-19877-1-git-send-email-michel.thierry@intel.com> <1435764490-12029-1-git-send-email-michel.thierry@intel.com> Cc: mesa-dev@lists.freedesktop.org, Ben Widawsky Subject: [Intel-gfx] [PATCH mesa v2] i965/gen8+: bo in state base address must be in 32-bit address range X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Gen8+ supports 48-bit virtual addresses, but some objects must always be allocated inside the 32-bit address range. In specific, any resource used with flat/heapless (0x00000000-0xfffff000) General State Heap or Intruction State Heap must be in a 32-bit range (GSH / ISH), because the General State Offset and Instruction State Offset are limited to 32-bits. Use drm_intel_bo_emit_reloc_48bit when the 4GB limit is not necessary, and the bo can be in the full address space. This commit introduces a dependency of libdrm 2.4.63, which introduces the drm_intel_bo_emit_reloc_48bit function. v2: s/48baddress/48b_address/, Only use in OUT_RELOC64 cases, OUT_RELOC implies a 32-bit address offset is needed (Ben) Cc: Ben Widawsky Cc: mesa-dev@lists.freedesktop.org Signed-off-by: Michel Thierry --- configure.ac | 2 +- src/mesa/drivers/dri/i965/gen8_misc_state.c | 23 +++++++++++++++-------- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 6 +++--- 3 files changed, 19 insertions(+), 12 deletions(-) diff --git a/configure.ac b/configure.ac index af61aa2..c92ca44 100644 --- a/configure.ac +++ b/configure.ac @@ -68,7 +68,7 @@ AC_SUBST([OSMESA_VERSION]) dnl Versions for external dependencies LIBDRM_REQUIRED=2.4.38 LIBDRM_RADEON_REQUIRED=2.4.56 -LIBDRM_INTEL_REQUIRED=2.4.60 +LIBDRM_INTEL_REQUIRED=2.4.63 LIBDRM_NVVIEUX_REQUIRED=2.4.33 LIBDRM_NOUVEAU_REQUIRED="2.4.33 libdrm >= 2.4.41" LIBDRM_FREEDRENO_REQUIRED=2.4.57 diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c b/src/mesa/drivers/dri/i965/gen8_misc_state.c index b20038e..5c8924d 100644 --- a/src/mesa/drivers/dri/i965/gen8_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c @@ -28,6 +28,11 @@ /** * Define the base addresses which some state is referenced from. + * + * Use OUT_RELOC instead of OUT_RELOC64, because the General State + * Offset and Instruction State Offset are limited to 32-bits by + * hardware [and add OUT_BATCH(0) after each OUT_RELOC to complete + * the number of dwords needed for STATE_BASE_ADDRESS]. */ void gen8_upload_state_base_address(struct brw_context *brw) { @@ -41,19 +46,21 @@ void gen8_upload_state_base_address(struct brw_context *brw) OUT_BATCH(0); OUT_BATCH(mocs_wb << 16); /* Surface state base address: */ - OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, - mocs_wb << 4 | 1); + OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, + mocs_wb << 4 | 1); + OUT_BATCH(0); /* Dynamic state base address: */ - OUT_RELOC64(brw->batch.bo, - I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0, - mocs_wb << 4 | 1); + OUT_RELOC(brw->batch.bo, + I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0, + mocs_wb << 4 | 1); + OUT_BATCH(0); /* Indirect object base address: MEDIA_OBJECT data */ OUT_BATCH(mocs_wb << 4 | 1); OUT_BATCH(0); /* Instruction base address: shader kernels (incl. SIP) */ - OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, - mocs_wb << 4 | 1); - + OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, + mocs_wb << 4 | 1); + OUT_BATCH(0); /* General state buffer size */ OUT_BATCH(0xfffff001); /* Dynamic state buffer size */ diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 54081a1..220a35b 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -411,9 +411,9 @@ intel_batchbuffer_emit_reloc64(struct brw_context *brw, uint32_t read_domains, uint32_t write_domain, uint32_t delta) { - int ret = drm_intel_bo_emit_reloc(brw->batch.bo, 4*brw->batch.used, - buffer, delta, - read_domains, write_domain); + int ret = drm_intel_bo_emit_reloc_48bit(brw->batch.bo, 4*brw->batch.used, + buffer, delta, + read_domains, write_domain); assert(ret == 0); (void) ret;