From patchwork Wed Jul 8 14:24:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 6747801 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 49E5D9F2F0 for ; Wed, 8 Jul 2015 14:24:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 34D8F20604 for ; Wed, 8 Jul 2015 14:24:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 00057205FE for ; Wed, 8 Jul 2015 14:24:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D54F6E628; Wed, 8 Jul 2015 07:24:14 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id AD3576E6B9 for ; Wed, 8 Jul 2015 07:24:13 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 08 Jul 2015 07:24:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,431,1432623600"; d="scan'208";a="758381749" Received: from amanna-desktop.iind.intel.com ([10.223.25.39]) by fmsmga002.fm.intel.com with ESMTP; 08 Jul 2015 07:24:12 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Wed, 8 Jul 2015 19:54:44 +0530 Message-Id: <1436365487-19242-4-git-send-email-animesh.manna@intel.com> X-Mailer: git-send-email 2.0.2 In-Reply-To: <1436365487-19242-1-git-send-email-animesh.manna@intel.com> References: <20150707131823.GT7568@phenom.ffwll.local> <1436365487-19242-1-git-send-email-animesh.manna@intel.com> Subject: [Intel-gfx] [PATCH 3/6] drm/i915/gen9: Replaced request_firmware_nowait() by request_firmware(). X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP v1: As per review comments from Daniel, replaced async firmware loading with request_firmware() which will load the dmc firmware and once firmware is loaded, dc5/dc6 register programming can be done in the same thread. Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/i915_drv.c | 3 -- drivers/gpu/drm/i915/intel_csr.c | 79 ++++++++++++++++----------------- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +- 4 files changed, 41 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 217efcb..18aaaf6 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1066,10 +1066,7 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv) static int skl_resume_prepare(struct drm_i915_private *dev_priv) { - struct drm_device *dev = dev_priv->dev; - skl_init_cdclk(dev_priv); - intel_csr_load_program(dev); return 0; } diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index f3b4a17..8e9395f 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -192,14 +192,6 @@ static char intel_get_substepping(struct drm_device *dev) return -ENODATA; } -/** - * intel_csr_load_program() - write the firmware from memory to register. - * @dev: drm device. - * - * CSR firmware is read from a .bin file and kept in internal memory one time. - * Everytime display comes back from low power state this function is called to - * copy the firmware from internal memory to registers. - */ void intel_csr_load_program(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -222,9 +214,9 @@ void intel_csr_load_program(struct drm_device *dev) } } -static void finish_csr_load(const struct firmware *fw, void *context) +static void finish_csr_load(const struct firmware *fw, + struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = context; struct drm_device *dev = dev_priv->dev; struct intel_css_header *css_header; struct intel_package_header *package_header; @@ -235,16 +227,15 @@ static void finish_csr_load(const struct firmware *fw, void *context) uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes; uint32_t i; __be32 *dmc_payload; - bool fw_loaded = false; if (!fw) { i915_firmware_load_error_print(csr->fw_path, 0); - goto out; + return; } if ((stepping == -ENODATA) || (substepping == -ENODATA)) { DRM_ERROR("Unknown stepping info, firmware loading failed\n"); - goto out; + return; } /* Extract CSS Header information*/ @@ -253,7 +244,7 @@ static void finish_csr_load(const struct firmware *fw, void *context) (css_header->header_len * 4)) { DRM_ERROR("Firmware has wrong CSS header length %u bytes\n", (css_header->header_len * 4)); - goto out; + return; } readcount += sizeof(struct intel_css_header); @@ -264,7 +255,7 @@ static void finish_csr_load(const struct firmware *fw, void *context) (package_header->header_len * 4)) { DRM_ERROR("Firmware has wrong package header length %u bytes\n", (package_header->header_len * 4)); - goto out; + return; } readcount += sizeof(struct intel_package_header); @@ -284,7 +275,7 @@ static void finish_csr_load(const struct firmware *fw, void *context) } if (dmc_offset == CSR_DEFAULT_FW_OFFSET) { DRM_ERROR("Firmware not supported for %c stepping\n", stepping); - goto out; + return; } readcount += dmc_offset; @@ -293,7 +284,7 @@ static void finish_csr_load(const struct firmware *fw, void *context) if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) { DRM_ERROR("Firmware has wrong dmc header length %u bytes\n", (dmc_header->header_len)); - goto out; + return; } readcount += sizeof(struct intel_dmc_header); @@ -301,7 +292,7 @@ static void finish_csr_load(const struct firmware *fw, void *context) if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) { DRM_ERROR("Firmware has wrong mmio count %u\n", dmc_header->mmio_count); - goto out; + return; } csr->mmio_count = dmc_header->mmio_count; for (i = 0; i < dmc_header->mmio_count; i++) { @@ -309,7 +300,7 @@ static void finish_csr_load(const struct firmware *fw, void *context) dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) { DRM_ERROR(" Firmware has wrong mmio address 0x%x\n", dmc_header->mmioaddr[i]); - goto out; + return; } csr->mmioaddr[i] = dmc_header->mmioaddr[i]; csr->mmiodata[i] = dmc_header->mmiodata[i]; @@ -319,14 +310,14 @@ static void finish_csr_load(const struct firmware *fw, void *context) nbytes = dmc_header->fw_size * 4; if (nbytes > CSR_MAX_FW_SIZE) { DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes); - goto out; + return; } csr->dmc_fw_size = dmc_header->fw_size; csr->dmc_payload = kmalloc(nbytes, GFP_KERNEL); if (!csr->dmc_payload) { DRM_ERROR("Memory allocation failed for dmc payload\n"); - goto out; + return; } dmc_payload = csr->dmc_payload; @@ -342,13 +333,36 @@ static void finish_csr_load(const struct firmware *fw, void *context) /* load csr program during system boot, as needed for DC states */ intel_csr_load_program(dev); - fw_loaded = true; DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path); -out: - if (fw_loaded) - intel_runtime_pm_put(dev_priv); +} +/** + * intel_display_load_csr() - write the firmware from memory to register. + * @dev: drm device. + * + * CSR firmware is read from a .bin file and kept in internal memory one time. + * Everytime display comes back from low power state this function is called to + * copy the firmware to registers. + */ + +void intel_display_load_csr(struct drm_i915_private *dev_priv) +{ + struct intel_csr *csr = &dev_priv->csr; + const struct firmware *fw; + int ret; + + /* CSR supported for platform, load firmware */ + ret = request_firmware(&fw, csr->fw_path, + &dev_priv->dev->pdev->dev); + + DRM_DEBUG_KMS("Loading %s\n", csr->fw_path); + + if (ret) { + i915_firmware_load_error_print(csr->fw_path, ret); + return; + } + finish_csr_load(fw, dev_priv); release_firmware(fw); } @@ -363,7 +377,6 @@ void intel_csr_ucode_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_csr *csr = &dev_priv->csr; - int ret; if (!HAS_CSR(dev)) return; @@ -377,20 +390,6 @@ void intel_csr_ucode_init(struct drm_device *dev) DRM_DEBUG_KMS("Loading %s\n", csr->fw_path); - /* - * Obtain a runtime pm reference, until CSR is loaded, - * to avoid entering runtime-suspend. - */ - intel_runtime_pm_get(dev_priv); - - /* CSR supported for platform, load firmware */ - ret = request_firmware_nowait(THIS_MODULE, true, csr->fw_path, - &dev_priv->dev->pdev->dev, - GFP_KERNEL, dev_priv, - finish_csr_load); - if (ret) { - i915_firmware_load_error_print(csr->fw_path, ret); - } INIT_WORK(&csr->csr_work, intel_csr_setdc_work_fn); } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index f437a90..b427407 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1163,7 +1163,7 @@ u32 skl_plane_ctl_rotation(unsigned int rotation); /* intel_csr.c */ void intel_csr_ucode_init(struct drm_device *dev); -void intel_csr_load_program(struct drm_device *dev); +void intel_display_load_csr(struct drm_i915_private *dev_priv); void intel_csr_ucode_fini(struct drm_device *dev); void assert_csr_loaded(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index f261558..01e046e 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -570,8 +570,7 @@ void intel_csr_setdc_work_fn(struct work_struct *__work) struct intel_csr *csr = &dev_priv->csr; if (csr->dc_state_req) { - - /* TODO: Load the dmc firmware. */ + intel_display_load_csr(dev_priv); if (IS_SKYLAKE(dev_priv->dev)) skl_enable_dc6(dev_priv);