@@ -1671,6 +1671,7 @@ struct i915_oa_rcs_node {
u32 offset;
bool discard;
u32 ctx_id;
+ u32 pid;
};
extern const struct i915_oa_reg i915_oa_3d_mux_config_hsw[];
@@ -1978,6 +1979,8 @@ struct drm_i915_private {
struct list_head node_list;
struct work_struct work_timer;
struct work_struct work_event_destroy;
+#define I915_OA_SAMPLE_PID (1<<0)
+ int sample_info_flags;
} oa_pmu;
void (*insert_profile_cmd[I915_PROFILE_MAX])
@@ -57,6 +57,8 @@ void i915_oa_insert_cmd(struct intel_ringbuffer *ringbuf, u32 ctx_id)
return;
}
entry->ctx_id = ctx_id;
+ if (dev_priv->oa_pmu.sample_info_flags & I915_OA_SAMPLE_PID)
+ entry->pid = current->pid;
i915_gem_request_assign(&entry->req, ring->outstanding_lazy_request);
spin_lock_irqsave(&dev_priv->oa_pmu.lock, lock_flags);
@@ -315,8 +317,9 @@ static void forward_one_oa_rcs_sample(struct drm_i915_private *dev_priv,
struct perf_sample_data data;
struct perf_event *event = dev_priv->oa_pmu.exclusive_event;
int format_size, snapshot_size;
- u8 *snapshot;
+ u8 *snapshot, *current_ptr;
struct drm_i915_oa_node_ctx_id *ctx_info;
+ struct drm_i915_oa_node_pid *pid_info;
struct perf_raw_record raw;
u64 snapshot_ts;
@@ -326,6 +329,14 @@ static void forward_one_oa_rcs_sample(struct drm_i915_private *dev_priv,
ctx_info = (struct drm_i915_oa_node_ctx_id *)(snapshot + format_size);
ctx_info->ctx_id = node->ctx_id;
+ current_ptr = snapshot + snapshot_size;
+
+ if (dev_priv->oa_pmu.sample_info_flags & I915_OA_SAMPLE_PID) {
+ pid_info = (struct drm_i915_oa_node_pid *)current_ptr;
+ pid_info->pid = node->pid;
+ snapshot_size += sizeof(*pid_info);
+ current_ptr = snapshot + snapshot_size;
+ }
/* Flush the periodic snapshots till the ts of this OA report */
snapshot_ts = *(u64 *)(snapshot + 4);
@@ -680,6 +691,9 @@ static int init_oa_rcs_buffer(struct perf_event *event)
node_size = dev_priv->oa_pmu.oa_rcs_buffer.format_size +
sizeof(struct drm_i915_oa_node_ctx_id);
+ if (dev_priv->oa_pmu.sample_info_flags & I915_OA_SAMPLE_PID)
+ node_size += sizeof(struct drm_i915_oa_node_pid);
+
/* node size has to be aligned to 64 bytes, since only 64 byte aligned
* addresses can be given to OA unit for dumping OA reports */
node_size = ALIGN(node_size, 64);
@@ -833,6 +847,9 @@ static int i915_oa_event_init(struct perf_event *event)
if (!capable(CAP_SYS_ADMIN))
return -EACCES;
dev_priv->oa_pmu.multiple_ctx_mode = true;
+ if (oa_attr.sample_pid)
+ dev_priv->oa_pmu.sample_info_flags |=
+ I915_OA_SAMPLE_PID;
}
report_format = oa_attr.format;
@@ -93,7 +93,8 @@ typedef struct _drm_i915_oa_attr {
__u64 single_context : 1,
multiple_context_mode:1,
- __reserved_1:62;
+ sample_pid:1,
+ __reserved_1:61;
} drm_i915_oa_attr_t;
/* Header for PERF_RECORD_DEVICE type events */
@@ -128,6 +129,11 @@ struct drm_i915_oa_node_ctx_id {
__u32 pad;
};
+struct drm_i915_oa_node_pid {
+ __u32 pid;
+ __u32 pad;
+};
+
/* Each region is a minimum of 16k, and there are at most 255 of them.
*/
#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use