| Message ID | 1438250675-22790-1-git-send-email-michel.thierry@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 7/30/2015 3:34 PM, Michel Thierry wrote: > Introduces the Page Map Level 4 (PML4), ie. the new top level structure > of the page tables. > > To facilitate testing, 48b mode will be available on Broadwell and > GEN9+, when i915.enable_ppgtt = 3. > > v2: Remove unnecessary CONFIG_X86_64 checks, ppgtt code is already > 32/64-bit safe (Chris). > v3: Add goto free_scratch in temp 48-bit mode init code (Akash). > v4: kfree the pdp until the 4lvl alloc/free patch (Akash). > > Cc: Akash Goel <akash.goel@intel.com> > Signed-off-by: Michel Thierry <michel.thierry@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 3 ++- > drivers/gpu/drm/i915/i915_gem_gtt.c | 36 +++++++++++++++++++++++------------- > drivers/gpu/drm/i915/i915_gem_gtt.h | 26 +++++++++++++++++++++----- > 3 files changed, 46 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 04aa34a..4729eaf 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2498,7 +2498,8 @@ struct drm_i915_cmd_table { > #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) > #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) > #define USES_PPGTT(dev) (i915.enable_ppgtt) > -#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2) > +#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) > +#define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) > > #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) > #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 7f71746..3288154 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -104,9 +104,12 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) > { > bool has_aliasing_ppgtt; > bool has_full_ppgtt; > + bool has_full_64bit_ppgtt; > > has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; > has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; > + has_full_64bit_ppgtt = (IS_BROADWELL(dev) || > + INTEL_INFO(dev)->gen >= 9) && false; /* FIXME: 64b */ Sorry for the late comment. Would it be better to move the changes done in this sanitize function to the later patch only 'Flip the 48b switch' ? As even with the removal of these changes, setting of enable_ppgtt to 3 would still be equivalent to the default mode (-1). What is really needed now is the definition of 'USES_FULL_48BIT_PPGTT' macro. Best regards Akash > > if (intel_vgpu_active(dev)) > has_full_ppgtt = false; /* emulation is too hard */ > @@ -125,6 +128,9 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) > if (enable_ppgtt == 2 && has_full_ppgtt) > return 2; > > + if (enable_ppgtt == 3 && has_full_64bit_ppgtt) > + return 3; > + > #ifdef CONFIG_INTEL_IOMMU > /* Disable ppgtt on SNB if VT-d is on. */ > if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { > @@ -689,9 +695,6 @@ gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, > pt_vaddr = NULL; > > for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { > - if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) > - break; > - > if (pt_vaddr == NULL) { > struct i915_page_directory *pd = pdp->page_directory[pdpe]; > struct i915_page_table *pt = pd->page_table[pde]; > @@ -1105,14 +1108,6 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) > return ret; > > ppgtt->base.start = 0; > - ppgtt->base.total = 1ULL << 32; > - if (IS_ENABLED(CONFIG_X86_32)) > - /* While we have a proliferation of size_t variables > - * we cannot represent the full ppgtt size on 32bit, > - * so limit it to the same size as the GGTT (currently > - * 2GiB). > - */ > - ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total; > ppgtt->base.cleanup = gen8_ppgtt_cleanup; > ppgtt->base.allocate_va_range = gen8_alloc_va_range; > ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; > @@ -1122,10 +1117,25 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) > > ppgtt->switch_mm = gen8_mm_switch; > > - ret = __pdp_init(false, &ppgtt->pdp); > + if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { > + ret = __pdp_init(false, &ppgtt->pdp); > > - if (ret) > + if (ret) > + goto free_scratch; > + > + ppgtt->base.total = 1ULL << 32; > + if (IS_ENABLED(CONFIG_X86_32)) > + /* While we have a proliferation of size_t variables > + * we cannot represent the full ppgtt size on 32bit, > + * so limit it to the same size as the GGTT (currently > + * 2GiB). > + */ > + ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total; > + } else { > + ppgtt->base.total = 1ULL << 48; > + ret = -EPERM; /* Not yet implemented */ > goto free_scratch; > + } > > return 0; > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h > index 87e389c..04bc66f 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.h > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h > @@ -88,9 +88,17 @@ typedef uint64_t gen8_pde_t; > * PDPE | PDE | PTE | offset > * The difference as compared to normal x86 3 level page table is the PDPEs are > * programmed via register. > + * > + * GEN8 48b legacy style address is defined as a 4 level page table: > + * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 > + * PML4E | PDPE | PDE | PTE | offset > */ > +#define GEN8_PML4ES_PER_PML4 512 > +#define GEN8_PML4E_SHIFT 39 > #define GEN8_PDPE_SHIFT 30 > -#define GEN8_PDPE_MASK 0x3 > +/* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page > + * tables */ > +#define GEN8_PDPE_MASK 0x1ff > #define GEN8_PDE_SHIFT 21 > #define GEN8_PDE_MASK 0x1ff > #define GEN8_PTE_SHIFT 12 > @@ -98,8 +106,8 @@ typedef uint64_t gen8_pde_t; > #define GEN8_LEGACY_PDPES 4 > #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) > > -/* FIXME: Next patch will use dev */ > -#define I915_PDPES_PER_PDP(dev) GEN8_LEGACY_PDPES > +#define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ > + GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) > > #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) > #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ > @@ -250,6 +258,13 @@ struct i915_page_directory_pointer { > struct i915_page_directory **page_directory; > }; > > +struct i915_pml4 { > + struct i915_page_dma base; > + > + DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); > + struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; > +}; > + > struct i915_address_space { > struct drm_mm mm; > struct drm_device *dev; > @@ -345,8 +360,9 @@ struct i915_hw_ppgtt { > struct drm_mm_node node; > unsigned long pd_dirty_rings; > union { > - struct i915_page_directory_pointer pdp; > - struct i915_page_directory pd; > + struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ > + struct i915_page_directory_pointer pdp; /* GEN8+ */ > + struct i915_page_directory pd; /* GEN6-7 */ > }; > > struct drm_i915_file_private *file_priv; >
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 04aa34a..4729eaf 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2498,7 +2498,8 @@ struct drm_i915_cmd_table { #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) #define USES_PPGTT(dev) (i915.enable_ppgtt) -#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2) +#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) +#define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 7f71746..3288154 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -104,9 +104,12 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) { bool has_aliasing_ppgtt; bool has_full_ppgtt; + bool has_full_64bit_ppgtt; has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; + has_full_64bit_ppgtt = (IS_BROADWELL(dev) || + INTEL_INFO(dev)->gen >= 9) && false; /* FIXME: 64b */ if (intel_vgpu_active(dev)) has_full_ppgtt = false; /* emulation is too hard */ @@ -125,6 +128,9 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) if (enable_ppgtt == 2 && has_full_ppgtt) return 2; + if (enable_ppgtt == 3 && has_full_64bit_ppgtt) + return 3; + #ifdef CONFIG_INTEL_IOMMU /* Disable ppgtt on SNB if VT-d is on. */ if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { @@ -689,9 +695,6 @@ gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, pt_vaddr = NULL; for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { - if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) - break; - if (pt_vaddr == NULL) { struct i915_page_directory *pd = pdp->page_directory[pdpe]; struct i915_page_table *pt = pd->page_table[pde]; @@ -1105,14 +1108,6 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) return ret; ppgtt->base.start = 0; - ppgtt->base.total = 1ULL << 32; - if (IS_ENABLED(CONFIG_X86_32)) - /* While we have a proliferation of size_t variables - * we cannot represent the full ppgtt size on 32bit, - * so limit it to the same size as the GGTT (currently - * 2GiB). - */ - ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total; ppgtt->base.cleanup = gen8_ppgtt_cleanup; ppgtt->base.allocate_va_range = gen8_alloc_va_range; ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; @@ -1122,10 +1117,25 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) ppgtt->switch_mm = gen8_mm_switch; - ret = __pdp_init(false, &ppgtt->pdp); + if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { + ret = __pdp_init(false, &ppgtt->pdp); - if (ret) + if (ret) + goto free_scratch; + + ppgtt->base.total = 1ULL << 32; + if (IS_ENABLED(CONFIG_X86_32)) + /* While we have a proliferation of size_t variables + * we cannot represent the full ppgtt size on 32bit, + * so limit it to the same size as the GGTT (currently + * 2GiB). + */ + ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total; + } else { + ppgtt->base.total = 1ULL << 48; + ret = -EPERM; /* Not yet implemented */ goto free_scratch; + } return 0; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 87e389c..04bc66f 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -88,9 +88,17 @@ typedef uint64_t gen8_pde_t; * PDPE | PDE | PTE | offset * The difference as compared to normal x86 3 level page table is the PDPEs are * programmed via register. + * + * GEN8 48b legacy style address is defined as a 4 level page table: + * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 + * PML4E | PDPE | PDE | PTE | offset */ +#define GEN8_PML4ES_PER_PML4 512 +#define GEN8_PML4E_SHIFT 39 #define GEN8_PDPE_SHIFT 30 -#define GEN8_PDPE_MASK 0x3 +/* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page + * tables */ +#define GEN8_PDPE_MASK 0x1ff #define GEN8_PDE_SHIFT 21 #define GEN8_PDE_MASK 0x1ff #define GEN8_PTE_SHIFT 12 @@ -98,8 +106,8 @@ typedef uint64_t gen8_pde_t; #define GEN8_LEGACY_PDPES 4 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) -/* FIXME: Next patch will use dev */ -#define I915_PDPES_PER_PDP(dev) GEN8_LEGACY_PDPES +#define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ + GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ @@ -250,6 +258,13 @@ struct i915_page_directory_pointer { struct i915_page_directory **page_directory; }; +struct i915_pml4 { + struct i915_page_dma base; + + DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); + struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; +}; + struct i915_address_space { struct drm_mm mm; struct drm_device *dev; @@ -345,8 +360,9 @@ struct i915_hw_ppgtt { struct drm_mm_node node; unsigned long pd_dirty_rings; union { - struct i915_page_directory_pointer pdp; - struct i915_page_directory pd; + struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ + struct i915_page_directory_pointer pdp; /* GEN8+ */ + struct i915_page_directory pd; /* GEN6-7 */ }; struct drm_i915_file_private *file_priv;
Introduces the Page Map Level 4 (PML4), ie. the new top level structure of the page tables. To facilitate testing, 48b mode will be available on Broadwell and GEN9+, when i915.enable_ppgtt = 3. v2: Remove unnecessary CONFIG_X86_64 checks, ppgtt code is already 32/64-bit safe (Chris). v3: Add goto free_scratch in temp 48-bit mode init code (Akash). v4: kfree the pdp until the 4lvl alloc/free patch (Akash). Cc: Akash Goel <akash.goel@intel.com> Signed-off-by: Michel Thierry <michel.thierry@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 3 ++- drivers/gpu/drm/i915/i915_gem_gtt.c | 36 +++++++++++++++++++++++------------- drivers/gpu/drm/i915/i915_gem_gtt.h | 26 +++++++++++++++++++++----- 3 files changed, 46 insertions(+), 19 deletions(-)