From patchwork Tue Aug 4 10:21:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: arun.siluvery@linux.intel.com X-Patchwork-Id: 6936061 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5A6CCC05AC for ; Tue, 4 Aug 2015 10:22:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 64FFD20456 for ; Tue, 4 Aug 2015 10:22:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2634D20452 for ; Tue, 4 Aug 2015 10:22:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5EEB66E897; Tue, 4 Aug 2015 03:22:02 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id D16496E897 for ; Tue, 4 Aug 2015 03:22:00 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP; 04 Aug 2015 03:22:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,608,1432623600"; d="scan'208";a="535718552" Received: from asiluver-linux.isw.intel.com ([10.102.226.117]) by FMSMGA003.fm.intel.com with ESMTP; 04 Aug 2015 03:21:57 -0700 From: Arun Siluvery To: intel-gfx@lists.freedesktop.org Date: Tue, 4 Aug 2015 11:21:53 +0100 Message-Id: <1438683713-5464-1-git-send-email-arun.siluvery@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1438629897-2993-3-git-send-email-arun.siluvery@linux.intel.com> References: <1438629897-2993-3-git-send-email-arun.siluvery@linux.intel.com> Cc: Ben Widawsky Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915:gen9: Add disable gather at set shader w/a X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This WA is implemented in init_context as well as WA batch init. There are also some dependent bits need to be set in other registers for this to be complete. v2: behaviour of disable gather at set shader bit can be specified by two different registers, use a better option (Ben). Cc: Ben Widawsky Cc: Joonas Lahtinen Signed-off-by: Arun Siluvery Reviewed-by: Ben Widawsky Tested-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_reg.h | 5 +++++ drivers/gpu/drm/i915/intel_lrc.c | 8 ++++++++ drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8991cd5..8719a5a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1721,6 +1721,10 @@ enum skl_disp_power_wells { #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */ #define FW_BLC 0x020d8 #define FW_BLC2 0x020dc +#define GEN7_RS_CHICKEN 0x20DC +#define GEN9_RS_CHICKEN_DISABLE_GATHER_AT_SHADER (1<<2) +#define GEN7_FF_SLICE_CHICKEN1 0x20E0 +#define GEN9_PER_CTX_DISABLE_GATHER_CONTROL (1<<15) #define FW_BLC_SELF 0x020e0 /* 915+ only */ #define FW_BLC_SELF_EN_MASK (1<<31) #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ @@ -5836,6 +5840,7 @@ enum skl_disp_power_wells { # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14) #define COMMON_SLICE_CHICKEN2 0x7014 +#define GEN9_DISABLE_GATHER_SET_SHADER_SLICE (1<<12) # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) #define HIZ_CHICKEN 0x7018 diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 9faad82..d3a03f3 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1292,6 +1292,14 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring, struct drm_device *dev = ring->dev; uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); + /* WA to reset "disable gather at set shader slice" bit */ + if (IS_SKYLAKE(dev)) { + wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); + wa_ctx_emit(batch, index, COMMON_SLICE_CHICKEN2); + wa_ctx_emit(batch, index, + _MASKED_BIT_DISABLE(GEN9_DISABLE_GATHER_SET_SHADER_SLICE)); + } + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) || (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) { diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index dcd1b8f..5e8e5f9 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -985,6 +985,17 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); + /* WA to gather at set shader - skl,bxt + * These are dependent bits need to be set for the WA. + */ + if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) > SKL_REVID_D0) || + (IS_BROXTON(dev) && INTEL_REVID(dev) > BXT_REVID_A0)) { + WA_SET_BIT_MASKED(GEN7_FF_SLICE_CHICKEN1, + GEN9_PER_CTX_DISABLE_GATHER_CONTROL); + WA_SET_BIT_MASKED(GEN7_RS_CHICKEN, + GEN9_RS_CHICKEN_DISABLE_GATHER_AT_SHADER); + } + return 0; } @@ -1068,6 +1079,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring) HDC_FENCE_DEST_SLM_DISABLE | HDC_BARRIER_PERFORMANCE_DISABLE); + /* WA to Disable gather at set shader - skl + * This bit needs to be reset in Per ctx WA batch and it is also + * dependent on other bits in different register, all of them need + * be set for the WA to be complete. + */ + WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, GEN9_DISABLE_GATHER_SET_SHADER_SLICE); + return skl_tune_iz_hashing(ring); }