From patchwork Thu Aug 6 11:23:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 6958301 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C1BCCC05AC for ; Thu, 6 Aug 2015 11:23:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F096D205FA for ; Thu, 6 Aug 2015 11:23:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E53CA2061D for ; Thu, 6 Aug 2015 11:23:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2D4756E531; Thu, 6 Aug 2015 04:22:59 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D08E6E531 for ; Thu, 6 Aug 2015 04:22:57 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 06 Aug 2015 04:22:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,622,1432623600"; d="scan'208";a="778058156" Received: from amanna-desktop.iind.intel.com ([10.223.25.39]) by fmsmga002.fm.intel.com with ESMTP; 06 Aug 2015 04:22:54 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Thu, 6 Aug 2015 16:53:37 +0530 Message-Id: <1438860217-5544-1-git-send-email-animesh.manna@intel.com> X-Mailer: git-send-email 2.0.2 In-Reply-To: <55C322D7.8010106@intel.com> References: <55C322D7.8010106@intel.com> Cc: Rajneesh Bhardwaj , Daniel Vetter Subject: [Intel-gfx] [SKL-DMC-BUGFIX 3/5] drm/i915/skl: Do not disable cdclk PLL if csr firmware is present X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP While display engine entering into low power state no need to disable cdclk pll as CSR firmware of dmc will take care. If pll is already enabled firmware execution sequence will be blocked. This is one of the criteria for dmc to work properly. v1: Initial version. v2: Based on review comment from Daniel added code commnent. Cc: Daniel Vetter Cc: Damien Lespiau Cc: Imre Deak Cc: Sunil Kamath Signed-off-by: Animesh Manna Signed-off-bt: Vathsala Nagaraju Signed-off-by: Rajneesh Bhardwaj --- drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index af0bcfe..1f8d704 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5675,10 +5675,16 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv) if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) DRM_ERROR("DBuf power disable timeout\n"); - /* disable DPLL0 */ - I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); - if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) - DRM_ERROR("Couldn't disable DPLL0\n"); + /* + * DMC assumes ownership of LCPLL and will get confused if we touch it. + */ + if (dev_priv->csr.dmc_payload) { + /* disable DPLL0 */ + I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & + ~LCPLL_PLL_ENABLE); + if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) + DRM_ERROR("Couldn't disable DPLL0\n"); + } intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); }