| Message ID | 1439892037-6269-1-git-send-email-sivakumar.thulasimani@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, 18 Aug 2015, Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> wrote: > From: "Thulasimani,Sivakumar" <sivakumar.thulasimani@intel.com> > > This patch removes TP3 support on CHV since there is no support > for HBR2 on this platform. > > v2: rename the function to indicate it checks source rates (Jani) > v3: update comment to indicate TP3 dependancy on HBR2 supported > hardware (Jani) > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> Pushed first three patches in the series to drm-intel-fixes, thanks for the patches and review. (The last patch is skl specific, I'll pick it up for v4.3 in drm-intel-next-fixes after a backmerge.) BR, Jani. > --- > drivers/gpu/drm/i915/intel_dp.c | 31 +++++++++++++++++++++++-------- > 1 file changed, 23 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 475d8cb..051614a 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1207,6 +1207,20 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) > return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; > } > > +static bool intel_dp_source_supports_hbr2(struct drm_device *dev) > +{ > + /* WaDisableHBR2:skl */ > + if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) > + return false; > + > + if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || > + (INTEL_INFO(dev)->gen >= 9)) > + return true; > + else > + return false; > +} > + > + > static int > intel_dp_source_rates(struct drm_device *dev, const int **source_rates) > { > @@ -1220,12 +1234,8 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates) > > *source_rates = default_rates; > > - /* WaDisableHBR2:skl */ > - if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) > - return (DP_LINK_BW_2_7 >> 3) + 1; > - > - if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || > - (INTEL_INFO(dev)->gen >= 9)) > + /* This depends on the fact that 5.4 is last value in the array */ > + if (intel_dp_source_supports_hbr2(dev)) > return (DP_LINK_BW_5_4 >> 3) + 1; > else > return (DP_LINK_BW_2_7 >> 3) + 1; > @@ -3923,10 +3933,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) > } > } > > - /* Training Pattern 3 support, both source and sink */ > + /* Training Pattern 3 support, Intel platforms that support HBR2 alone > + * have support for TP3 hence that check is used along with dpcd check > + * to ensure TP3 can be enabled. > + * SKL < B0: due it's WaDisableHBR2 is the only exception where TP3 is > + * supported but still not enabled. > + */ > if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && > intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED && > - (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) { > + intel_dp_source_supports_hbr2(dev)) { > intel_dp->use_tps3 = true; > DRM_DEBUG_KMS("Displayport TPS3 supported\n"); > } else > -- > 1.7.9.5 >
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 475d8cb..051614a 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1207,6 +1207,20 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; } +static bool intel_dp_source_supports_hbr2(struct drm_device *dev) +{ + /* WaDisableHBR2:skl */ + if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) + return false; + + if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || + (INTEL_INFO(dev)->gen >= 9)) + return true; + else + return false; +} + + static int intel_dp_source_rates(struct drm_device *dev, const int **source_rates) { @@ -1220,12 +1234,8 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates) *source_rates = default_rates; - /* WaDisableHBR2:skl */ - if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) - return (DP_LINK_BW_2_7 >> 3) + 1; - - if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || - (INTEL_INFO(dev)->gen >= 9)) + /* This depends on the fact that 5.4 is last value in the array */ + if (intel_dp_source_supports_hbr2(dev)) return (DP_LINK_BW_5_4 >> 3) + 1; else return (DP_LINK_BW_2_7 >> 3) + 1; @@ -3923,10 +3933,15 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) } } - /* Training Pattern 3 support, both source and sink */ + /* Training Pattern 3 support, Intel platforms that support HBR2 alone + * have support for TP3 hence that check is used along with dpcd check + * to ensure TP3 can be enabled. + * SKL < B0: due it's WaDisableHBR2 is the only exception where TP3 is + * supported but still not enabled. + */ if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED && - (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) { + intel_dp_source_supports_hbr2(dev)) { intel_dp->use_tps3 = true; DRM_DEBUG_KMS("Displayport TPS3 supported\n"); } else