From patchwork Thu Aug 20 01:02:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chandra Konduru X-Patchwork-Id: 7040111 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B2E7BC05AC for ; Thu, 20 Aug 2015 01:05:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BD3BC2073E for ; Thu, 20 Aug 2015 01:05:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C7A74205E1 for ; Thu, 20 Aug 2015 01:04:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 400A16EC5A; Wed, 19 Aug 2015 18:04:59 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id BF9B86EC5E for ; Wed, 19 Aug 2015 18:04:57 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 19 Aug 2015 18:04:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,713,1432623600"; d="scan'208";a="787174796" Received: from cmkondur-desk2.fm.intel.com ([10.19.83.92]) by fmsmga002.fm.intel.com with ESMTP; 19 Aug 2015 18:04:57 -0700 From: Chandra Konduru To: intel-gfx@lists.freedesktop.org Date: Wed, 19 Aug 2015 18:02:36 -0700 Message-Id: <1440032556-9920-16-git-send-email-chandra.konduru@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1440032556-9920-1-git-send-email-chandra.konduru@intel.com> References: <1440032556-9920-1-git-send-email-chandra.konduru@intel.com> Cc: daniel.vetter@intel.com, ville.syrjala@intel.com Subject: [Intel-gfx] [PATCH 15/15] drm/i915: Add 90/270 rotation for NV12 format. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adding NV12 90/270 rotation support for primary and sprite planes. v2: -For 90/270 adjust pixel boundary only in Y-direction (bspec) v3: -Rebased (me) Signed-off-by: Chandra Konduru Testcase: igt/kms_nv12 --- drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++------ drivers/gpu/drm/i915/intel_sprite.c | 56 ++++++++++++++++++++++------------ 2 files changed, 56 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2158b8f..19d0f8b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3096,7 +3096,8 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, int src_x = 0, src_y = 0, src_w = 0, src_h = 0; int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; int scaler_id = -1; - u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; + unsigned long aux_dist = 0; + u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; u32 tile_row_adjustment = 0; u32 hphase = 0, vphase = 0; @@ -3155,12 +3156,16 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, x_offset = stride * tile_height - y - src_h; y_offset = x; plane_size = (src_w - 1) << 16 | (src_h - 1); - /* - * TBD: For NV12 90/270 rotation, Y and UV subplanes should - * be treated as separate surfaces and GTT remapping for - * rotation should be done separately for each subplane. - * Enable support once seperate remappings are available. - */ + + if (fb->pixel_format == DRM_FORMAT_NV12) { + u32 uv_tile_height = intel_tile_height(dev, fb->pixel_format, + fb->modifier[0], 1); + aux_stride = DIV_ROUND_UP(fb->height / 2, uv_tile_height); + aux_dist = intel_plane_obj_offset(to_intel_plane(plane), obj, 1) - + surf_addr; + aux_x_offset = aux_stride * uv_tile_height - y / 2 - fb->height / 2; + aux_y_offset = x / 2; + } } else { stride = fb->pitches[0] / stride_div; x_offset = x; @@ -11697,8 +11702,13 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, /* Adjust (macro)pixel boundary */ if (fb && intel_format_is_yuv(fb->pixel_format)) { - to_intel_plane_state(plane_state)->src.x1 &= ~0x10000; - to_intel_plane_state(plane_state)->src.x2 &= ~0x10000; + if (intel_rotation_90_or_270(plane_state->rotation)) { + to_intel_plane_state(plane_state)->src.y1 &= ~0x10000; + to_intel_plane_state(plane_state)->src.y2 &= ~0x10000; + } else { + to_intel_plane_state(plane_state)->src.x1 &= ~0x10000; + to_intel_plane_state(plane_state)->src.x2 &= ~0x10000; + } } if (crtc_state && INTEL_INFO(dev)->gen >= 9 && diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 9d1c5b9..3522cb0 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -188,7 +188,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, int x_offset, y_offset; struct intel_crtc_state *crtc_state = to_intel_crtc(crtc)->config; int scaler_id; - u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; + unsigned long aux_dist = 0; + u32 aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; u32 tile_row_adjustment = 0; u32 hphase = 0, vphase = 0; @@ -238,12 +239,14 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, x_offset = stride * tile_height - y - (src_h + 1); y_offset = x; - /* - * TBD: For NV12 90/270 rotation, Y and UV subplanes should - * be treated as separate surfaces and GTT remapping for - * rotation should be done separately for each subplane. - * Enable support once seperate remappings are available. - */ + if (fb->pixel_format == DRM_FORMAT_NV12) { + u32 uv_tile_height = intel_tile_height(dev, fb->pixel_format, + fb->modifier[0], 1); + aux_stride = DIV_ROUND_UP(fb->height / 2, uv_tile_height); + aux_dist = intel_plane_obj_offset(intel_plane, obj, 1) - surf_addr; + aux_x_offset = aux_stride * uv_tile_height - y / 2 - fb->height / 2; + aux_y_offset = x / 2; + } } else { stride = fb->pitches[0] / stride_div; plane_size = (src_h << 16) | src_w; @@ -900,18 +903,33 @@ intel_check_sprite_plane(struct drm_plane *plane, src_h = drm_rect_height(src) >> 16; if (intel_format_is_yuv(fb->pixel_format)) { - src_x &= ~1; - src_w &= ~1; - - /* - * Must keep src and dst the - * same if we can't scale. - */ - if (!can_scale) - crtc_w &= ~1; - - if (crtc_w == 0) - state->visible = false; + if (intel_rotation_90_or_270(state->base.rotation)) { + src_y &= ~1; + src_h &= ~1; + + /* + * Must keep src and dst the + * same if we can't scale. + */ + if (!can_scale) + crtc_h &= ~1; + + if (crtc_h == 0) + state->visible = false; + } else { + src_x &= ~1; + src_w &= ~1; + + /* + * Must keep src and dst the + * same if we can't scale. + */ + if (!can_scale) + crtc_w &= ~1; + + if (crtc_w == 0) + state->visible = false; + } } }