| Message ID | 1440533169-32265-6-git-send-email-animesh.manna@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wednesday 26 August 2015 01:36 AM, Animesh Manna wrote: > Another interesting criteria to work dmc as expected is pw1 to be > enabled by driver and dmc will shut it off in its execution > sequence. If already disabled by driver dmc will get confuse and > behave differently than expected found during pc10 entry issue > for skl. > > So berfore we disable power-well 1, added check if dmc firmware is > present and driver will not disable power well 1, but for any reason > if firmware is not present of failed to load we can shut off the > power well 1 which will save some power. > > As skl is currently fully dependent on dmc to go in lowest possible > power state (dc6) but the same is not applicable for bxt. Display > engine can enter into dc9 without dmc, hence unblocking disable call. > > v1: Initial version. > > v2: Rebased as per current patch series. > > Cc: Daniel Vetter <daniel.vetter@intel.com> > Cc: Damien Lespiau <damien.lespiau@intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Sunil Kamath <sunil.kamath@intel.com> > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 23a3aa3..340f386 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -652,9 +652,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, > } > } else { > if (enable_requested) { > - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); > - POSTING_READ(HSW_PWR_WELL_DRIVER); > - DRM_DEBUG_KMS("Disabling %s\n", power_well->name); > + if (IS_SKYLAKE(dev) && > + (power_well->data == SKL_DISP_PW_1) && > + (intel_csr_load_status_get(dev_priv) == FW_LOADED)) > + DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n"); > + else { > + I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); > + POSTING_READ(HSW_PWR_WELL_DRIVER); > + DRM_DEBUG_KMS("Disabling %s\n", power_well->name); > + } > > if (GEN9_ENABLE_DC5(dev) && > power_well->data == SKL_DISP_PW_2) { Valid fix and patch is ready for merge now. Reviewed-by: A.Sunil Kamath <sunil.kamath@intel.com> <mailto:sunil.kamath@intel.com>
On Mon, Sep 07, 2015 at 04:39:19PM +0530, Sunil Kamath wrote: > On Wednesday 26 August 2015 01:36 AM, Animesh Manna wrote: > >Another interesting criteria to work dmc as expected is pw1 to be > >enabled by driver and dmc will shut it off in its execution > >sequence. If already disabled by driver dmc will get confuse and > >behave differently than expected found during pc10 entry issue > >for skl. > > > >So berfore we disable power-well 1, added check if dmc firmware is > >present and driver will not disable power well 1, but for any reason > >if firmware is not present of failed to load we can shut off the > >power well 1 which will save some power. > > > >As skl is currently fully dependent on dmc to go in lowest possible > >power state (dc6) but the same is not applicable for bxt. Display > >engine can enter into dc9 without dmc, hence unblocking disable call. > > > >v1: Initial version. > > > >v2: Rebased as per current patch series. > > > >Cc: Daniel Vetter <daniel.vetter@intel.com> > >Cc: Damien Lespiau <damien.lespiau@intel.com> > >Cc: Imre Deak <imre.deak@intel.com> > >Cc: Sunil Kamath <sunil.kamath@intel.com> > >Signed-off-by: Animesh Manna <animesh.manna@intel.com> > >Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> > >--- > > drivers/gpu/drm/i915/intel_runtime_pm.c | 12 +++++++++--- > > 1 file changed, 9 insertions(+), 3 deletions(-) > > > >diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > >index 23a3aa3..340f386 100644 > >--- a/drivers/gpu/drm/i915/intel_runtime_pm.c > >+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > >@@ -652,9 +652,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, > > } > > } else { > > if (enable_requested) { > >- I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); > >- POSTING_READ(HSW_PWR_WELL_DRIVER); > >- DRM_DEBUG_KMS("Disabling %s\n", power_well->name); > >+ if (IS_SKYLAKE(dev) && > >+ (power_well->data == SKL_DISP_PW_1) && > >+ (intel_csr_load_status_get(dev_priv) == FW_LOADED)) > >+ DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n"); > >+ else { > >+ I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); > >+ POSTING_READ(HSW_PWR_WELL_DRIVER); > >+ DRM_DEBUG_KMS("Disabling %s\n", power_well->name); > >+ } > > if (GEN9_ENABLE_DC5(dev) && > > power_well->data == SKL_DISP_PW_2) { > > Valid fix and patch is ready for merge now. > > Reviewed-by: A.Sunil Kamath <sunil.kamath@intel.com> Ok I pulled them all in except patch 3. -Daniel
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 23a3aa3..340f386 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -652,9 +652,15 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv, } } else { if (enable_requested) { - I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); - POSTING_READ(HSW_PWR_WELL_DRIVER); - DRM_DEBUG_KMS("Disabling %s\n", power_well->name); + if (IS_SKYLAKE(dev) && + (power_well->data == SKL_DISP_PW_1) && + (intel_csr_load_status_get(dev_priv) == FW_LOADED)) + DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n"); + else { + I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); + POSTING_READ(HSW_PWR_WELL_DRIVER); + DRM_DEBUG_KMS("Disabling %s\n", power_well->name); + } if (GEN9_ENABLE_DC5(dev) && power_well->data == SKL_DISP_PW_2) {