| Message ID | 1440747679-20716-6-git-send-email-zhiyuan.lv@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On pe, 2015-08-28 at 15:41 +0800, Zhiyuan Lv wrote: > When i915 drivers run inside a VM with Intel GVT-g, some explicit > notifications are needed from guest to host device model through PV > INFO page write. The notifications include: > > PPGTT create > PPGTT destroy > > They are used for the shadow implementation of PPGTT. Intel GVT-g > needs to write-protect the guest pages of PPGTT, and clear the write > protection when they end their life cycle. > > v2: > - Use lower_32_bits()/upper_32_bits() for qword operations; > - Remove the notification of guest context creation/destroy; > > Signed-off-by: Zhiyuan Lv <zhiyuan.lv@intel.com> > Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> > Again, as there's really no formal spec of what the hypervisor expects to see, that part is hard to comment on, so apart from that: Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> PS. Adding people who previously commented on the patch as CC, makes the reviewing go much smoother (new revisions get picked up faster). > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 41 > +++++++++++++++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 56cc8e8..df60227 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -899,6 +899,41 @@ static int gen8_init_scratch(struct > i915_address_space *vm) > return 0; > } > > +static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool > create) > +{ > + enum vgt_g2v_type msg; > + struct drm_device *dev = ppgtt->base.dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + unsigned int offset = vgtif_reg(pdp0_lo); > + int i; > + > + if (USES_FULL_48BIT_PPGTT(dev)) { > + u64 daddr = px_dma(&ppgtt->pml4); > + > + I915_WRITE(offset, lower_32_bits(daddr)); > + I915_WRITE(offset + 4, upper_32_bits(daddr)); > + > + msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : > + VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY) > ; > + } else { > + for (i = 0; i < GEN8_LEGACY_PDPES; i++) { > + u64 daddr = i915_page_dir_dma_addr(ppgtt, > i); > + > + I915_WRITE(offset, lower_32_bits(daddr)); > + I915_WRITE(offset + 4, > upper_32_bits(daddr)); > + > + offset += 8; > + } > + > + msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : > + VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY) > ; > + } > + > + I915_WRITE(vgtif_reg(g2v_notify), msg); > + > + return 0; > +} > + > static void gen8_free_scratch(struct i915_address_space *vm) > { > struct drm_device *dev = vm->dev; > @@ -945,6 +980,9 @@ static void gen8_ppgtt_cleanup(struct > i915_address_space *vm) > struct i915_hw_ppgtt *ppgtt = > container_of(vm, struct i915_hw_ppgtt, base); > > + if (intel_vgpu_active(vm->dev)) > + gen8_ppgtt_notify_vgt(ppgtt, false); > + > if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) > gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt > ->pdp); > else > @@ -1519,6 +1557,9 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt > *ppgtt) > } > } > > + if (intel_vgpu_active(ppgtt->base.dev)) > + gen8_ppgtt_notify_vgt(ppgtt, true); > + > return 0; > > free_scratch:
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 56cc8e8..df60227 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -899,6 +899,41 @@ static int gen8_init_scratch(struct i915_address_space *vm) return 0; } +static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) +{ + enum vgt_g2v_type msg; + struct drm_device *dev = ppgtt->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + unsigned int offset = vgtif_reg(pdp0_lo); + int i; + + if (USES_FULL_48BIT_PPGTT(dev)) { + u64 daddr = px_dma(&ppgtt->pml4); + + I915_WRITE(offset, lower_32_bits(daddr)); + I915_WRITE(offset + 4, upper_32_bits(daddr)); + + msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : + VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); + } else { + for (i = 0; i < GEN8_LEGACY_PDPES; i++) { + u64 daddr = i915_page_dir_dma_addr(ppgtt, i); + + I915_WRITE(offset, lower_32_bits(daddr)); + I915_WRITE(offset + 4, upper_32_bits(daddr)); + + offset += 8; + } + + msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : + VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); + } + + I915_WRITE(vgtif_reg(g2v_notify), msg); + + return 0; +} + static void gen8_free_scratch(struct i915_address_space *vm) { struct drm_device *dev = vm->dev; @@ -945,6 +980,9 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm) struct i915_hw_ppgtt *ppgtt = container_of(vm, struct i915_hw_ppgtt, base); + if (intel_vgpu_active(vm->dev)) + gen8_ppgtt_notify_vgt(ppgtt, false); + if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp); else @@ -1519,6 +1557,9 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) } } + if (intel_vgpu_active(ppgtt->base.dev)) + gen8_ppgtt_notify_vgt(ppgtt, true); + return 0; free_scratch: