diff mbox

[14/16] drm/i915: skl nv12 wa - disable streamer fix

Message ID 1441071321-419-15-git-send-email-chandra.konduru@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Chandra Konduru Sept. 1, 2015, 1:35 a.m. UTC 
When the plane source pixel format is NV12, the CHICKEN_PIPESL
register bit 22 must be set to 1

v2:
-one wa per commit with comments, and function headers (Daniel)

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |   12 ++++++++
 drivers/gpu/drm/i915/intel_csr.c     |   29 ------------------
 drivers/gpu/drm/i915/intel_display.c |   54 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |    2 ++
 drivers/gpu/drm/i915/intel_sprite.c  |   11 +++++++
 5 files changed, 79 insertions(+), 29 deletions(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c4d732f..84c5db6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5354,6 +5354,18 @@  enum skl_disp_power_wells {
 #define PLANE_NV12_BUF_CFG(pipe, plane)	\
 	_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
 
+/*
+ * Skylake Chicken registers
+ */
+#define _CHICKEN_PIPESL_A          0x420B0
+#define _CHICKEN_PIPESL_B          0x420B4
+#define _CHICKEN_PIPESL_C          0x420B8
+#define  DISABLE_STREAMER_FIX      (1 << 22)
+#define CHICKEN_PIPESL(pipe) _PIPE(pipe, _CHICKEN_PIPESL_A, _CHICKEN_PIPESL_B)
+
+#define CHICKEN_DCPR_1             0x46430
+#define IDLE_WAKEMEM_MASK          (1 << 13)
+
 /* SKL new cursor registers */
 #define _CUR_BUF_CFG_A				0x7017c
 #define _CUR_BUF_CFG_B				0x7117c
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index ba1ae03..9577727 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -170,35 +170,6 @@  struct intel_dmc_header {
 	uint32_t reserved1[2];
 } __packed;
 
-struct stepping_info {
-	char stepping;
-	char substepping;
-};
-
-static const struct stepping_info skl_stepping_info[] = {
-		{'A', '0'}, {'B', '0'}, {'C', '0'},
-		{'D', '0'}, {'E', '0'}, {'F', '0'},
-		{'G', '0'}, {'H', '0'}, {'I', '0'}
-};
-
-static char intel_get_stepping(struct drm_device *dev)
-{
-	if (IS_SKYLAKE(dev) && (dev->pdev->revision <
-			ARRAY_SIZE(skl_stepping_info)))
-		return skl_stepping_info[dev->pdev->revision].stepping;
-	else
-		return -ENODATA;
-}
-
-static char intel_get_substepping(struct drm_device *dev)
-{
-	if (IS_SKYLAKE(dev) && (dev->pdev->revision <
-			ARRAY_SIZE(skl_stepping_info)))
-		return skl_stepping_info[dev->pdev->revision].substepping;
-	else
-		return -ENODATA;
-}
-
 /**
  * intel_csr_load_status_get() - to get firmware loading status.
  * @dev_priv: i915 device.
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 419660d..35e9f89 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -92,6 +92,19 @@  static const uint32_t intel_cursor_formats[] = {
 	DRM_FORMAT_ARGB8888,
 };
 
+/* stepping info */
+struct stepping_info {
+	char stepping;
+	char substepping;
+};
+
+/* skl stepping info */
+static const struct stepping_info skl_stepping_info[] = {
+	{'A', '0'}, {'B', '0'}, {'C', '0'},
+	{'D', '0'}, {'E', '0'}, {'F', '0'},
+	{'G', '0'}, {'H', '0'}, {'I', '0'},
+};
+
 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 
 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
@@ -138,6 +151,36 @@  struct intel_limit {
 	intel_p2_t	    p2;
 };
 
+/**
+ * intel_get_stepping() - get stepping info
+ * @dev: drm device.
+ *
+ * Returns stepping id 'A', 'B', 'C', etc.
+ */
+char intel_get_stepping(struct drm_device *dev)
+{
+	if (IS_SKYLAKE(dev) && (dev->pdev->revision <
+			ARRAY_SIZE(skl_stepping_info)))
+		return skl_stepping_info[dev->pdev->revision].stepping;
+	else
+		return -ENODATA;
+}
+
+/**
+ * intel_get_substepping() - get substepping info
+ * @dev: drm device.
+ *
+ * Returns substepping id '0', '1', '2', etc.
+ */
+char intel_get_substepping(struct drm_device *dev)
+{
+	if (IS_SKYLAKE(dev) && (dev->pdev->revision <
+			ARRAY_SIZE(skl_stepping_info)))
+		return skl_stepping_info[dev->pdev->revision].substepping;
+	else
+		return -ENODATA;
+}
+
 int
 intel_pch_rawclk(struct drm_device *dev)
 {
@@ -3196,6 +3239,17 @@  static void skylake_update_primary_plane(struct drm_crtc *crtc,
 	I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride);
 	I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset << 16 | aux_x_offset);
 
+	/*
+	 * Per bspec, for SKL C and BXT A steppings, when the plane source pixel
+	 * format is NV12, the CHICKEN_PIPESL register bit 22 must be set to 1
+	 */
+	if (((IS_SKYLAKE(dev) && intel_get_stepping(dev) == 'C') ||
+		(IS_BROXTON(dev) && intel_get_stepping(dev) == 'A')) &&
+		fb->pixel_format == DRM_FORMAT_NV12) {
+			I915_WRITE(CHICKEN_PIPESL(pipe),
+				I915_READ(CHICKEN_PIPESL(pipe)) | DISABLE_STREAMER_FIX);
+	}
+
 	if (scaler_id >= 0) {
 		uint32_t ps_ctrl = 0;
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d50b8cb..59549245 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -992,6 +992,8 @@  void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
 /* intel_display.c */
 extern const struct drm_plane_funcs intel_plane_funcs;
 bool intel_has_pending_fb_unpin(struct drm_device *dev);
+char intel_get_stepping(struct drm_device *dev);
+char intel_get_substepping(struct drm_device *dev);
 int intel_pch_rawclk(struct drm_device *dev);
 void intel_mark_busy(struct drm_device *dev);
 void intel_mark_idle(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 0ea9273..b2346b0 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -278,6 +278,17 @@  skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 	I915_WRITE(PLANE_AUX_DIST(pipe, plane), aux_dist | aux_stride);
 	I915_WRITE(PLANE_AUX_OFFSET(pipe, plane), aux_y_offset<<16 | aux_x_offset);
 
+	/*
+	 * Per bspec, for SKL C and BXT A steppings, when the plane source pixel
+	 * format is NV12, the CHICKEN_PIPESL register bit 22 must be set to 1
+	 */
+	if (((IS_SKYLAKE(dev) && intel_get_stepping(dev) == 'C') ||
+		(IS_BROXTON(dev) && intel_get_stepping(dev) == 'A')) &&
+		fb->pixel_format == DRM_FORMAT_NV12) {
+			I915_WRITE(CHICKEN_PIPESL(pipe),
+				I915_READ(CHICKEN_PIPESL(pipe)) | DISABLE_STREAMER_FIX);
+	}
+
 	/* program plane scaler */
 	if (scaler_id >= 0) {
 		uint32_t ps_ctrl = 0;