From patchwork Tue Sep 1 01:35:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chandra Konduru X-Patchwork-Id: 7102201 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9445E9F1D5 for ; Tue, 1 Sep 2015 01:37:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8BA982062E for ; Tue, 1 Sep 2015 01:37:30 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7B2152051F for ; Tue, 1 Sep 2015 01:37:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF30672055; Mon, 31 Aug 2015 18:37:28 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id B4D787207F for ; Mon, 31 Aug 2015 18:37:25 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 31 Aug 2015 18:37:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,445,1437462000"; d="scan'208";a="795390577" Received: from cmkondur-desk2.fm.intel.com ([10.19.83.165]) by fmsmga002.fm.intel.com with ESMTP; 31 Aug 2015 18:37:25 -0700 From: Chandra Konduru To: intel-gfx@lists.freedesktop.org Date: Mon, 31 Aug 2015 18:35:19 -0700 Message-Id: <1441071321-419-15-git-send-email-chandra.konduru@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1441071321-419-1-git-send-email-chandra.konduru@intel.com> References: <1441071321-419-1-git-send-email-chandra.konduru@intel.com> Cc: daniel.vetter@intel.com, ville.syrjala@intel.com Subject: [Intel-gfx] [PATCH 14/16] drm/i915: skl nv12 wa - disable streamer fix X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When the plane source pixel format is NV12, the CHICKEN_PIPESL register bit 22 must be set to 1 v2: -one wa per commit with comments, and function headers (Daniel) Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++ drivers/gpu/drm/i915/intel_csr.c | 29 ------------------ drivers/gpu/drm/i915/intel_display.c | 54 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_sprite.c | 11 +++++++ 5 files changed, 79 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c4d732f..84c5db6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5354,6 +5354,18 @@ enum skl_disp_power_wells { #define PLANE_NV12_BUF_CFG(pipe, plane) \ _PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) +/* + * Skylake Chicken registers + */ +#define _CHICKEN_PIPESL_A 0x420B0 +#define _CHICKEN_PIPESL_B 0x420B4 +#define _CHICKEN_PIPESL_C 0x420B8 +#define DISABLE_STREAMER_FIX (1 << 22) +#define CHICKEN_PIPESL(pipe) _PIPE(pipe, _CHICKEN_PIPESL_A, _CHICKEN_PIPESL_B) + +#define CHICKEN_DCPR_1 0x46430 +#define IDLE_WAKEMEM_MASK (1 << 13) + /* SKL new cursor registers */ #define _CUR_BUF_CFG_A 0x7017c #define _CUR_BUF_CFG_B 0x7117c diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index ba1ae03..9577727 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -170,35 +170,6 @@ struct intel_dmc_header { uint32_t reserved1[2]; } __packed; -struct stepping_info { - char stepping; - char substepping; -}; - -static const struct stepping_info skl_stepping_info[] = { - {'A', '0'}, {'B', '0'}, {'C', '0'}, - {'D', '0'}, {'E', '0'}, {'F', '0'}, - {'G', '0'}, {'H', '0'}, {'I', '0'} -}; - -static char intel_get_stepping(struct drm_device *dev) -{ - if (IS_SKYLAKE(dev) && (dev->pdev->revision < - ARRAY_SIZE(skl_stepping_info))) - return skl_stepping_info[dev->pdev->revision].stepping; - else - return -ENODATA; -} - -static char intel_get_substepping(struct drm_device *dev) -{ - if (IS_SKYLAKE(dev) && (dev->pdev->revision < - ARRAY_SIZE(skl_stepping_info))) - return skl_stepping_info[dev->pdev->revision].substepping; - else - return -ENODATA; -} - /** * intel_csr_load_status_get() - to get firmware loading status. * @dev_priv: i915 device. diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 419660d..35e9f89 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -92,6 +92,19 @@ static const uint32_t intel_cursor_formats[] = { DRM_FORMAT_ARGB8888, }; +/* stepping info */ +struct stepping_info { + char stepping; + char substepping; +}; + +/* skl stepping info */ +static const struct stepping_info skl_stepping_info[] = { + {'A', '0'}, {'B', '0'}, {'C', '0'}, + {'D', '0'}, {'E', '0'}, {'F', '0'}, + {'G', '0'}, {'H', '0'}, {'I', '0'}, +}; + static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); static void i9xx_crtc_clock_get(struct intel_crtc *crtc, @@ -138,6 +151,36 @@ struct intel_limit { intel_p2_t p2; }; +/** + * intel_get_stepping() - get stepping info + * @dev: drm device. + * + * Returns stepping id 'A', 'B', 'C', etc. + */ +char intel_get_stepping(struct drm_device *dev) +{ + if (IS_SKYLAKE(dev) && (dev->pdev->revision < + ARRAY_SIZE(skl_stepping_info))) + return skl_stepping_info[dev->pdev->revision].stepping; + else + return -ENODATA; +} + +/** + * intel_get_substepping() - get substepping info + * @dev: drm device. + * + * Returns substepping id '0', '1', '2', etc. + */ +char intel_get_substepping(struct drm_device *dev) +{ + if (IS_SKYLAKE(dev) && (dev->pdev->revision < + ARRAY_SIZE(skl_stepping_info))) + return skl_stepping_info[dev->pdev->revision].substepping; + else + return -ENODATA; +} + int intel_pch_rawclk(struct drm_device *dev) { @@ -3196,6 +3239,17 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, I915_WRITE(PLANE_AUX_DIST(pipe, 0), aux_dist | aux_stride); I915_WRITE(PLANE_AUX_OFFSET(pipe, 0), aux_y_offset << 16 | aux_x_offset); + /* + * Per bspec, for SKL C and BXT A steppings, when the plane source pixel + * format is NV12, the CHICKEN_PIPESL register bit 22 must be set to 1 + */ + if (((IS_SKYLAKE(dev) && intel_get_stepping(dev) == 'C') || + (IS_BROXTON(dev) && intel_get_stepping(dev) == 'A')) && + fb->pixel_format == DRM_FORMAT_NV12) { + I915_WRITE(CHICKEN_PIPESL(pipe), + I915_READ(CHICKEN_PIPESL(pipe)) | DISABLE_STREAMER_FIX); + } + if (scaler_id >= 0) { uint32_t ps_ctrl = 0; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d50b8cb..59549245 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -992,6 +992,8 @@ void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); /* intel_display.c */ extern const struct drm_plane_funcs intel_plane_funcs; bool intel_has_pending_fb_unpin(struct drm_device *dev); +char intel_get_stepping(struct drm_device *dev); +char intel_get_substepping(struct drm_device *dev); int intel_pch_rawclk(struct drm_device *dev); void intel_mark_busy(struct drm_device *dev); void intel_mark_idle(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 0ea9273..b2346b0 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -278,6 +278,17 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, I915_WRITE(PLANE_AUX_DIST(pipe, plane), aux_dist | aux_stride); I915_WRITE(PLANE_AUX_OFFSET(pipe, plane), aux_y_offset<<16 | aux_x_offset); + /* + * Per bspec, for SKL C and BXT A steppings, when the plane source pixel + * format is NV12, the CHICKEN_PIPESL register bit 22 must be set to 1 + */ + if (((IS_SKYLAKE(dev) && intel_get_stepping(dev) == 'C') || + (IS_BROXTON(dev) && intel_get_stepping(dev) == 'A')) && + fb->pixel_format == DRM_FORMAT_NV12) { + I915_WRITE(CHICKEN_PIPESL(pipe), + I915_READ(CHICKEN_PIPESL(pipe)) | DISABLE_STREAMER_FIX); + } + /* program plane scaler */ if (scaler_id >= 0) { uint32_t ps_ctrl = 0;