From patchwork Tue Sep 1 01:35:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chandra Konduru X-Patchwork-Id: 7102231 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E45BDBF036 for ; Tue, 1 Sep 2015 01:37:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 12F612062F for ; Tue, 1 Sep 2015 01:37:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6D1032055D for ; Tue, 1 Sep 2015 01:37:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BE7097207A; Mon, 31 Aug 2015 18:37:32 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id E42FD72055 for ; Mon, 31 Aug 2015 18:37:26 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 31 Aug 2015 18:37:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,445,1437462000"; d="scan'208";a="795390606" Received: from cmkondur-desk2.fm.intel.com ([10.19.83.165]) by fmsmga002.fm.intel.com with ESMTP; 31 Aug 2015 18:37:26 -0700 From: Chandra Konduru To: intel-gfx@lists.freedesktop.org Date: Mon, 31 Aug 2015 18:35:20 -0700 Message-Id: <1441071321-419-16-git-send-email-chandra.konduru@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1441071321-419-1-git-send-email-chandra.konduru@intel.com> References: <1441071321-419-1-git-send-email-chandra.konduru@intel.com> Cc: daniel.vetter@intel.com, ville.syrjala@intel.com Subject: [Intel-gfx] [PATCH 15/16] drm/i915: skl nv12 wa - NV12 to RGB switch X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Switching format from NV12 to RGB can result in display underrun and corruption. This workaround sets bits 15 & 19 to 1 in CLKGATE_DIS_PSL register to address transition underrun. Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 84c5db6..3192837 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5366,6 +5366,14 @@ enum skl_disp_power_wells { #define CHICKEN_DCPR_1 0x46430 #define IDLE_WAKEMEM_MASK (1 << 13) +#define CLKGATE_DIS_PSL_A 0x46520 +#define CLKGATE_DIS_PSL_B 0x46524 +#define CLKGATE_DIS_PSL_C 0x46528 +#define DUPS1_GATING_DIS (1 << 15) +#define DUPS2_GATING_DIS (1 << 19) +#define DUPS3_GATING_DIS (1 << 23) +#define CLKGATE_DIS_PSL(pipe) _PIPE(pipe, CLKGATE_DIS_PSL_A, CLKGATE_DIS_PSL_B) + /* SKL new cursor registers */ #define _CUR_BUF_CFG_A 0x7017c #define _CUR_BUF_CFG_B 0x7117c diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 35e9f89..e8fb15b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5058,6 +5058,25 @@ static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; } +/* + * Switching format from NV12 to RGB can result in display underrun + * and corruption. Workaround is to set bits 15 & 19 to 1 in + * CLKGATE_DIS_PSL register. + */ +static void skl_wa_clkgate(struct drm_i915_private *dev_priv, + int pipe, int enable) +{ + if (pipe == PIPE_A || pipe == PIPE_B) { + if (enable) + I915_WRITE(CLKGATE_DIS_PSL(pipe), + DUPS1_GATING_DIS | DUPS2_GATING_DIS); + else + I915_WRITE(CLKGATE_DIS_PSL(pipe), + I915_READ(CLKGATE_DIS_PSL(pipe) & + ~(DUPS1_GATING_DIS|DUPS2_GATING_DIS))); + } +} + static void haswell_crtc_enable(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; @@ -5148,6 +5167,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_wait_for_vblank(dev, hsw_workaround_pipe); intel_wait_for_vblank(dev, hsw_workaround_pipe); } + + /* workaround for NV12 */ + skl_wa_clkgate(dev_priv, pipe, 1); } static void ironlake_pfit_disable(struct intel_crtc *crtc) @@ -5265,6 +5287,9 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) intel_crtc->active = false; intel_update_watermarks(crtc); + + /* workaround for NV12 */ + skl_wa_clkgate(dev_priv, intel_crtc->pipe, 0); } static void i9xx_pfit_enable(struct intel_crtc *crtc)