From patchwork Thu Sep 3 16:13:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 7117811 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A74309F1CD for ; Thu, 3 Sep 2015 16:14:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CD005207DE for ; Thu, 3 Sep 2015 16:14:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E0AFC207D7 for ; Thu, 3 Sep 2015 16:14:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0418D7216A; Thu, 3 Sep 2015 09:14:15 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id F0FAB7216A for ; Thu, 3 Sep 2015 09:14:13 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 03 Sep 2015 09:14:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,463,1437462000"; d="scan'208";a="761687743" Received: from dceraolo-linux2.isw.intel.com ([10.102.226.112]) by orsmga001.jf.intel.com with ESMTP; 03 Sep 2015 09:14:11 -0700 From: daniele.ceraolospurio@intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Sep 2015 17:13:58 +0100 Message-Id: <1441296838-14072-1-git-send-email-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 1.9.1 Subject: [Intel-gfx] [PATCH i-g-t] tests/gem_bad_reloc: use correct page table size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Daniele Ceraolo Spurio 2 subparts of gem_bad_reloc check that the reloc address is below the global gtt boundary. However, when executing from ppgtt the reloc address can be greater than that and still be a valid address. To be sure that we're using the right upper limit, select it based on the ppgtt mode. Cc: Michel Thierry Signed-off-by: Daniele Ceraolo Spurio Reviewed-by: Michel Thierry --- tests/gem_bad_reloc.c | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/tests/gem_bad_reloc.c b/tests/gem_bad_reloc.c index 563571e..d2e0b70 100644 --- a/tests/gem_bad_reloc.c +++ b/tests/gem_bad_reloc.c @@ -44,6 +44,32 @@ IGT_TEST_DESCRIPTION("Simulates SNA behaviour using negative self-relocations" #define USE_LUT (1 << 12) +static uint64_t get_page_table_size(int fd) +{ + struct drm_i915_getparam gp; + int val = 0; + + memset(&gp, 0, sizeof(gp)); + gp.param = 18; /* HAS_ALIASING_PPGTT */ + gp.value = &val; + + if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp)) + return 0; + errno = 0; + + switch (val) { + case 0: + case 1: + return gem_aperture_size(fd); + case 2: + return 1ULL << 32; + case 3: + return 1ULL << 48; + } + + return 0; +} + /* Simulates SNA behaviour using negative self-relocations for * STATE_BASE_ADDRESS command packets. If they wrap around (to values greater * than the total size of the GTT), the GPU will hang. @@ -54,7 +80,7 @@ static int negative_reloc(int fd, unsigned flags) struct drm_i915_gem_execbuffer2 execbuf; struct drm_i915_gem_exec_object2 gem_exec[2]; struct drm_i915_gem_relocation_entry gem_reloc[1000]; - uint64_t gtt_max = gem_aperture_size(fd); + uint64_t gtt_max = get_page_table_size(fd); uint32_t buf[1024] = {MI_BATCH_BUFFER_END}; int i; @@ -86,7 +112,7 @@ static int negative_reloc(int fd, unsigned flags) &execbuf)); gem_close(fd, gem_exec[1].handle); - igt_info("Found offset %ld for 4k batch\n", (long)gem_exec[0].offset); + igt_info("Found offset %lld for 4k batch\n", (long long)gem_exec[0].offset); /* * Ideally we'd like to be able to control where the kernel is going to * place the buffer. We don't SKIP here because it causes the test @@ -114,7 +140,7 @@ static int negative_reloc(int fd, unsigned flags) DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf)); - igt_info("Batch is now at offset %ld\n", (long)gem_exec[0].offset); + igt_info("Batch is now at offset %lld\n", (long long)gem_exec[0].offset); gem_read(fd, gem_exec[0].handle, 0, buf, sizeof(buf)); gem_close(fd, gem_exec[0].handle);