From patchwork Thu Sep 3 19:51:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zanoni, Paulo R" X-Patchwork-Id: 7118951 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A7449BEEC1 for ; Thu, 3 Sep 2015 19:52:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B9FC0207C5 for ; Thu, 3 Sep 2015 19:52:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id AF2612079C for ; Thu, 3 Sep 2015 19:52:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 33CEB6E891; Thu, 3 Sep 2015 12:52:03 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 6549D6E891 for ; Thu, 3 Sep 2015 12:52:02 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP; 03 Sep 2015 12:52:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,463,1437462000"; d="scan'208";a="797724748" Received: from bpilney-mobl1.amr.corp.intel.com (HELO panetone.amr.corp.intel.com) ([10.255.92.27]) by fmsmga002.fm.intel.com with ESMTP; 03 Sep 2015 12:52:01 -0700 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Thu, 3 Sep 2015 16:51:45 -0300 Message-Id: <1441309905-2744-5-git-send-email-paulo.r.zanoni@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1441309905-2744-1-git-send-email-paulo.r.zanoni@intel.com> References: <1441309905-2744-1-git-send-email-paulo.r.zanoni@intel.com> Cc: Daniel Vetter , Mika Kuoppala Subject: [Intel-gfx] [PATCH 4/4] drm/i915: Reduce frequency of unspecific HSW reg debugging X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Chris Wilson Delay the expensive read on the FPGA_DBG register from once per mmio to once per forcewake section when we are doing the general wellbeing check rather than the targetted error detection. This almost reduces the overhead of the debug facility (for example when submitting execlists) to zero whilst keeping the debug checks around. v2: Enable one-shot mmio debugging from the interrupt check as well as a safeguard to catch invalid display writes from outside the powerwell. v3 (from Paulo): rebase since gen9 addition and intel_uncore_check_errors removal Signed-off-by: Chris Wilson Cc: Daniel Vetter Cc: Mika Kuoppala Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_uncore.c | 52 +++++++++++++++++++++---------------- 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 8844c314..1fe63fc 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -148,6 +148,31 @@ fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_doma } static void +hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv) +{ + static bool mmio_debug_once = true; + + if (i915.mmio_debug || !mmio_debug_once) + return; + + if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { + DRM_ERROR("Unclaimed register detected, " + "enabling oneshot unclaimed register reporting. " + "Please use i915.mmio_debug=N for more information.\n"); + __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); + i915.mmio_debug = mmio_debug_once--; + } +} + +static void +fw_domains_put_debug(struct drm_i915_private *dev_priv, + enum forcewake_domains fw_domains) +{ + hsw_unclaimed_reg_detect(dev_priv); + fw_domains_put(dev_priv, fw_domains); +} + +static void fw_domains_posting_read(struct drm_i915_private *dev_priv) { struct intel_uncore_forcewake_domain *d; @@ -627,26 +652,6 @@ hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read, } } -static void -hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv, u32 reg) -{ - static bool mmio_debug_once = true; - - if (!UNCLAIMED_CHECK_RANGE(reg)) - return; - - if (i915.mmio_debug || !mmio_debug_once) - return; - - if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { - DRM_ERROR("Unclaimed register detected, " - "enabling oneshot unclaimed register reporting. " - "Please use i915.mmio_debug=N for more information.\n"); - __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); - i915.mmio_debug = mmio_debug_once--; - } -} - #define GEN2_READ_HEADER(x) \ u##x val = 0; \ assert_device_not_suspended(dev_priv); @@ -900,7 +905,6 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) gen6_gt_check_fifodbg(dev_priv); \ } \ hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ - hsw_unclaimed_reg_detect(dev_priv, reg); \ GEN6_WRITE_FOOTER; \ } @@ -942,7 +946,6 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ __raw_i915_write##x(dev_priv, reg, val); \ hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ - hsw_unclaimed_reg_detect(dev_priv, reg); \ GEN6_WRITE_FOOTER; \ } @@ -1008,7 +1011,6 @@ gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \ __force_wake_get(dev_priv, fw_engine); \ __raw_i915_write##x(dev_priv, reg, val); \ hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ - hsw_unclaimed_reg_detect(dev_priv, reg); \ GEN6_WRITE_FOOTER; \ } @@ -1194,6 +1196,10 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev) FORCEWAKE, FORCEWAKE_ACK); } + if (HAS_FPGA_DBG_UNCLAIMED(dev) && + dev_priv->uncore.funcs.force_wake_put == fw_domains_put) + dev_priv->uncore.funcs.force_wake_put = fw_domains_put_debug; + /* All future platforms are expected to require complex power gating */ WARN_ON(dev_priv->uncore.fw_domains == 0); }