From patchwork Sat Sep 5 02:33:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chandra Konduru X-Patchwork-Id: 7127111 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 88F6BBF036 for ; Sat, 5 Sep 2015 02:35:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9D79A208CD for ; Sat, 5 Sep 2015 02:35:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A58FF208C8 for ; Sat, 5 Sep 2015 02:35:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 346F26EC54; Fri, 4 Sep 2015 19:35:11 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 35C526EC53 for ; Fri, 4 Sep 2015 19:35:09 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP; 04 Sep 2015 19:35:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,472,1437462000"; d="scan'208";a="798725929" Received: from cmkondur-desk2.fm.intel.com ([10.19.83.165]) by fmsmga002.fm.intel.com with ESMTP; 04 Sep 2015 19:35:09 -0700 From: Chandra Konduru To: intel-gfx@lists.freedesktop.org Date: Fri, 4 Sep 2015 19:33:08 -0700 Message-Id: <1441420391-19109-13-git-send-email-chandra.konduru@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1441420391-19109-1-git-send-email-chandra.konduru@intel.com> References: <1441420391-19109-1-git-send-email-chandra.konduru@intel.com> Cc: daniel.vetter@intel.com, ville.syrjala@intel.com Subject: [Intel-gfx] [PATCH 12/15] drm/i915: Set initial phase & trip for NV12 scaler X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch sets default initial phase and trip to scale NV12 content. In future, if needed these can be set via properties or other means depending on incoming stream request. Until then defaults are fine. Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/intel_display.c | 7 +++++++ drivers/gpu/drm/i915/intel_sprite.c | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6714066..3296d16 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3098,6 +3098,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, int scaler_id = -1; u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; u32 tile_row_adjustment = 0; + u32 hphase = 0, vphase = 0; plane_state = to_intel_plane_state(plane->state); @@ -3181,6 +3182,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, /* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */ aux_stride = fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED ? DIV_ROUND_UP(stride, 2) : stride; + + hphase = 0x00010001; /* use trip for both Y and UV */ + vphase = 0x00012000; /* use trip for Y and phase 0.5 for UV */ } } plane_offset = y_offset << 16 | x_offset; @@ -3209,6 +3213,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); } + I915_WRITE(SKL_PS_HPHASE(pipe, scaler_id), hphase); + I915_WRITE(SKL_PS_VPHASE(pipe, scaler_id), vphase); + I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); POSTING_READ(PLANE_SURF(pipe, 0)); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 347fb1f..5ca62b6 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -190,6 +190,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, int scaler_id; u32 aux_dist = 0, aux_x_offset = 0, aux_y_offset = 0, aux_stride = 0; u32 tile_row_adjustment = 0; + u32 hphase = 0, vphase = 0; plane_ctl = PLANE_CTL_ENABLE | PLANE_CTL_PIPE_CSC_ENABLE; @@ -264,6 +265,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, /* For tile-Yf, uv-subplane tile width is 2x of Y-subplane */ aux_stride = fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED ? DIV_ROUND_UP(stride, 2) : stride; + + hphase = 0x00010001; /* use trip for both Y and UV */ + vphase = 0x00012000; /* use trip for Y and phase 0.5 for UV */ } } plane_offset = y_offset << 16 | x_offset; @@ -292,6 +296,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); } + I915_WRITE(SKL_PS_HPHASE(pipe, scaler_id), hphase); + I915_WRITE(SKL_PS_VPHASE(pipe, scaler_id), vphase); + I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); POSTING_READ(PLANE_SURF(pipe, plane));