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[14/15] drm/i915: skl nv12 wa - NV12 to RGB switch

Message ID 1441420391-19109-15-git-send-email-chandra.konduru@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Chandra Konduru Sept. 5, 2015, 2:33 a.m. UTC 
Switching format from NV12 to RGB can result in display underrun
and corruption. This workaround sets bits 15 & 19 to 1 in
CLKGATE_DIS_PSL register to address transition underrun.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    8 ++++++++
 drivers/gpu/drm/i915/intel_display.c |   25 +++++++++++++++++++++++++
 2 files changed, 33 insertions(+)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d20f235..2e2636d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5366,6 +5366,14 @@  enum skl_disp_power_wells {
 #define CHICKEN_DCPR_1             0x46430
 #define IDLE_WAKEMEM_MASK          (1 << 13)
 
+#define CLKGATE_DIS_PSL_A        0x46520
+#define CLKGATE_DIS_PSL_B        0x46524
+#define CLKGATE_DIS_PSL_C        0x46528
+#define DUPS1_GATING_DIS         (1 << 15)
+#define DUPS2_GATING_DIS         (1 << 19)
+#define DUPS3_GATING_DIS         (1 << 23)
+#define CLKGATE_DIS_PSL(pipe)  _PIPE(pipe, CLKGATE_DIS_PSL_A, CLKGATE_DIS_PSL_B)
+
 /* SKL new cursor registers */
 #define _CUR_BUF_CFG_A				0x7017c
 #define _CUR_BUF_CFG_B				0x7117c
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9e11439..457b79b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5017,6 +5017,25 @@  static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
 	return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
 }
 
+/*
+ * Switching format from NV12 to RGB can result in display underrun
+ * and corruption. Workaround is to set bits 15 & 19 to 1 in
+ * CLKGATE_DIS_PSL register.
+ */
+static void skl_wa_clkgate(struct drm_i915_private *dev_priv,
+	int pipe, int enable)
+{
+	if (pipe == PIPE_A || pipe == PIPE_B) {
+		if (enable)
+			I915_WRITE(CLKGATE_DIS_PSL(pipe),
+				DUPS1_GATING_DIS | DUPS2_GATING_DIS);
+		else
+			I915_WRITE(CLKGATE_DIS_PSL(pipe),
+				I915_READ(CLKGATE_DIS_PSL(pipe) &
+				~(DUPS1_GATING_DIS|DUPS2_GATING_DIS)));
+	}
+}
+
 static void haswell_crtc_enable(struct drm_crtc *crtc)
 {
 	struct drm_device *dev = crtc->dev;
@@ -5107,6 +5126,9 @@  static void haswell_crtc_enable(struct drm_crtc *crtc)
 		intel_wait_for_vblank(dev, hsw_workaround_pipe);
 		intel_wait_for_vblank(dev, hsw_workaround_pipe);
 	}
+
+	/* workaround for NV12 */
+	skl_wa_clkgate(dev_priv, pipe, 1);
 }
 
 static void ironlake_pfit_disable(struct intel_crtc *crtc)
@@ -5224,6 +5246,9 @@  static void haswell_crtc_disable(struct drm_crtc *crtc)
 
 	intel_crtc->active = false;
 	intel_update_watermarks(crtc);
+
+	/* workaround for NV12 */
+	skl_wa_clkgate(dev_priv, intel_crtc->pipe, 0);
 }
 
 static void i9xx_pfit_enable(struct intel_crtc *crtc)