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[2/6] drm/i915/bxt: Add WaSetClckGatingDisableMedia

Message ID 1441704713-21575-2-git-send-email-arun.siluvery@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

arun.siluvery@linux.intel.com Sept. 8, 2015, 9:31 a.m. UTC
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
 2 files changed, 7 insertions(+)

Comments

sagar.a.kamble@intel.com Sept. 12, 2015, 4:03 p.m. UTC | #1
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

On 9/8/2015 3:01 PM, Arun Siluvery wrote:
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 1 +
>   drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>   2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84ed9ab..2c719b0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6894,6 +6894,7 @@ enum skl_disp_power_wells {
>   #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1<<0)
>   #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1<<2)
>   #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1<<4)
> +#define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1<<6)
>   
>   #define GEN8_GARBCNTL                   0xB004
>   #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 64bc77e..920872a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -134,6 +134,12 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>   		 */
>   		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
>   	}
> +
> +	/* WaSetClckGatingDisableMedia:bxt */
> +	if (INTEL_REVID(dev) == BXT_REVID_A0) {
> +		I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
> +					    ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
> +	}
>   }
>   
>   static void i915_pineview_get_mem_freq(struct drm_device *dev)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84ed9ab..2c719b0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6894,6 +6894,7 @@  enum skl_disp_power_wells {
 #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1<<0)
 #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1<<2)
 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1<<4)
+#define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1<<6)
 
 #define GEN8_GARBCNTL                   0xB004
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 64bc77e..920872a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -134,6 +134,12 @@  static void bxt_init_clock_gating(struct drm_device *dev)
 		 */
 		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 	}
+
+	/* WaSetClckGatingDisableMedia:bxt */
+	if (INTEL_REVID(dev) == BXT_REVID_A0) {
+		I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
+					    ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
+	}
 }
 
 static void i915_pineview_get_mem_freq(struct drm_device *dev)