| Message ID | 1441704713-21575-6-git-send-email-arun.siluvery@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> On 9/8/2015 3:01 PM, Arun Siluvery wrote: > From: Nick Hoath <nicholas.hoath@intel.com> > > Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c > index 5eafd31..e0601cc 100644 > --- a/drivers/gpu/drm/i915/intel_guc_loader.c > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c > @@ -330,6 +330,13 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv) > /* Enable MIA caching. GuC clock gating is disabled. */ > I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE); > > + /* WaDisableMinuteIaClockGating:skl,bxt */ > + if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || > + (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) { > + I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) & > + ~GUC_ENABLE_MIA_CLOCK_GATING)); > + } > + > /* WaC6DisallowByGfxPause*/ > I915_WRITE(GEN6_GFXPAUSE, 0x30FFF); >
On Sat, Sep 12, 2015 at 11:26:38PM +0530, Kamble, Sagar A wrote: > Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> > > On 9/8/2015 3:01 PM, Arun Siluvery wrote: > >From: Nick Hoath <nicholas.hoath@intel.com> > > > >Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> > >Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Applied 3 patches from this series with Sagar's review-by. Thanks, Daniel > >--- > > drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > >diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c > >index 5eafd31..e0601cc 100644 > >--- a/drivers/gpu/drm/i915/intel_guc_loader.c > >+++ b/drivers/gpu/drm/i915/intel_guc_loader.c > >@@ -330,6 +330,13 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv) > > /* Enable MIA caching. GuC clock gating is disabled. */ > > I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE); > >+ /* WaDisableMinuteIaClockGating:skl,bxt */ > >+ if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || > >+ (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) { > >+ I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) & > >+ ~GUC_ENABLE_MIA_CLOCK_GATING)); > >+ } > >+ > > /* WaC6DisallowByGfxPause*/ > > I915_WRITE(GEN6_GFXPAUSE, 0x30FFF); > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 5eafd31..e0601cc 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -330,6 +330,13 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv) /* Enable MIA caching. GuC clock gating is disabled. */ I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE); + /* WaDisableMinuteIaClockGating:skl,bxt */ + if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || + (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) { + I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) & + ~GUC_ENABLE_MIA_CLOCK_GATING)); + } + /* WaC6DisallowByGfxPause*/ I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);