From patchwork Tue Sep 8 12:27:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 7140631 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 773CEBEEC1 for ; Tue, 8 Sep 2015 12:28:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ACDCC206EA for ; Tue, 8 Sep 2015 12:28:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D0AB4206EB for ; Tue, 8 Sep 2015 12:28:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D5CB6E38D; Tue, 8 Sep 2015 05:28:13 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 059426E38D for ; Tue, 8 Sep 2015 05:28:11 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 08 Sep 2015 05:28:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,489,1437462000"; d="scan'208";a="764637928" Received: from linux.intel.com ([10.23.219.25]) by orsmga001.jf.intel.com with ESMTP; 08 Sep 2015 05:28:11 -0700 Received: from localhost (aconselv-mobl3.ger.corp.intel.com [10.252.9.149]) by linux.intel.com (Postfix) with ESMTP id 4B79C6A4083; Tue, 8 Sep 2015 05:27:18 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Tue, 8 Sep 2015 15:27:54 +0300 Message-Id: <1441715280-11623-4-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1441715280-11623-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1441715280-11623-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: jani.nikula@intel.com, Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH 3/8] drm/i915: Split intel_dp_update_link_train() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Separate the bit that writes to DP register in its own function and move the update of the train_set based on the adjust request to the sink out. The objective is to split the generic link training logic from the i915 specific part. --- drivers/gpu/drm/i915/intel_dp.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 58efdca..d7988a6 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3640,20 +3640,25 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp, return intel_dp_set_link_train(intel_dp, dp_train_pat); } -static bool -intel_dp_update_link_train(struct intel_dp *intel_dp, - const uint8_t link_status[DP_LINK_STATUS_SIZE]) +static void +intel_dp_update_signal_levels(struct intel_dp *intel_dp) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); - int ret; - intel_get_adjust_train(intel_dp, link_status); intel_dp_set_signal_levels(intel_dp, &intel_dp->DP); I915_WRITE(intel_dp->output_reg, intel_dp->DP); POSTING_READ(intel_dp->output_reg); +} + +static bool +intel_dp_update_link_train(struct intel_dp *intel_dp) +{ + int ret; + + intel_dp_update_signal_levels(intel_dp); ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, intel_dp->train_set, intel_dp->lane_count); @@ -3796,7 +3801,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; /* Update training set as requested by target */ - if (!intel_dp_update_link_train(intel_dp, link_status)) { + intel_get_adjust_train(intel_dp, link_status); + if (!intel_dp_update_link_train(intel_dp)) { DRM_ERROR("failed to update link training\n"); break; } @@ -3885,7 +3891,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) } /* Update training set as requested by target */ - if (!intel_dp_update_link_train(intel_dp, link_status)) { + intel_get_adjust_train(intel_dp, link_status); + if (!intel_dp_update_link_train(intel_dp)) { DRM_ERROR("failed to update link training\n"); break; }