From patchwork Wed Sep 9 22:59:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chandra Konduru X-Patchwork-Id: 7149651 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E91E0BEEC1 for ; Wed, 9 Sep 2015 23:00:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EDA1F20645 for ; Wed, 9 Sep 2015 23:00:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D1C262063F for ; Wed, 9 Sep 2015 23:00:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E271F6E2EF; Wed, 9 Sep 2015 16:00:46 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 875CF6E2EF for ; Wed, 9 Sep 2015 16:00:45 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP; 09 Sep 2015 16:00:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,499,1437462000"; d="scan'208";a="641824708" Received: from cmkondur-desk2.fm.intel.com ([10.19.83.171]) by orsmga003.jf.intel.com with ESMTP; 09 Sep 2015 16:00:45 -0700 From: Chandra Konduru To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Sep 2015 15:59:03 -0700 Message-Id: <1441839543-20005-1-git-send-email-chandra.konduru@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1441420391-19109-10-git-send-email-chandra.konduru@intel.com> References: <1441420391-19109-10-git-send-email-chandra.konduru@intel.com> Cc: daniel.vetter@intel.com, ville.syrjala@intel.com Subject: [Intel-gfx] [PATCH 09/15] drm/i915: Add NV12 support to intel_framebuffer_init X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (me) v3: -cosmetic update, split checks into two (Ville) v4: -Add stride alignment and modifier checks for UV subplane (Ville) Signed-off-by: Chandra Konduru Testcase: igt/kms_nv12 --- drivers/gpu/drm/i915/intel_display.c | 67 ++++++++++++++++++++++++++++------ drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_sprite.c | 2 +- 3 files changed, 57 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 84dad95..6124339 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2906,9 +2906,9 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc, } u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, - uint32_t pixel_format) + uint32_t pixel_format, int plane) { - u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; + u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, plane) * 8; /* * The stride is either expressed as a multiple of 64 bytes @@ -3117,7 +3117,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, obj = intel_fb_obj(fb); stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], - fb->pixel_format); + fb->pixel_format, 0); surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); /* @@ -9101,7 +9101,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, val = I915_READ(PLANE_STRIDE(pipe, 0)); stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], - fb->pixel_format); + fb->pixel_format, 0); fb->pitches[0] = (val & 0x3ff) * stride_mult; aligned_height = intel_fb_align_height(dev, fb->height, @@ -11172,7 +11172,7 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) */ stride = fb->pitches[0] / intel_fb_stride_alignment(dev, fb->modifier[0], - fb->pixel_format); + fb->pixel_format, 0); /* * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on @@ -14238,6 +14238,7 @@ static int intel_framebuffer_init(struct drm_device *dev, { unsigned int aligned_height; int ret; + int i; u32 pitch_limit, stride_alignment; WARN_ON(!mutex_is_locked(&dev->struct_mutex)); @@ -14277,12 +14278,15 @@ static int intel_framebuffer_init(struct drm_device *dev, return -EINVAL; } - stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], - mode_cmd->pixel_format); - if (mode_cmd->pitches[0] & (stride_alignment - 1)) { - DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", - mode_cmd->pitches[0], stride_alignment); - return -EINVAL; + /* check stride alignment for sub-planes */ + for (i = 0; i < drm_format_num_planes(mode_cmd->pixel_format); i++) { + stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[i], + mode_cmd->pixel_format, i); + if (mode_cmd->pitches[i] & (stride_alignment - 1)) { + DRM_DEBUG("subplane %d pitch (%d) must be at least %u bytes " + "aligned\n", i, mode_cmd->pitches[i], stride_alignment); + return -EINVAL; + } } pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], @@ -14349,9 +14353,48 @@ static int intel_framebuffer_init(struct drm_device *dev, return -EINVAL; } break; + case DRM_FORMAT_NV12: + if (INTEL_INFO(dev)->gen < 9) { + DRM_DEBUG("unsupported pixel format: %s\n", + drm_get_format_name(mode_cmd->pixel_format)); + return -EINVAL; + } + if (obj->tiling_mode == I915_TILING_X && + !(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) { + mode_cmd->modifier[1] = I915_FORMAT_MOD_X_TILED; + } + if (!mode_cmd->offsets[1]) { + DRM_DEBUG("uv start offset not set\n"); + return -EINVAL; + } + if (mode_cmd->pitches[0] != mode_cmd->pitches[1]) { + DRM_DEBUG("y and uv subplanes have different pitches\n"); + return -EINVAL; + } + if (mode_cmd->handles[0] != mode_cmd->handles[1]) { + DRM_DEBUG("y and uv subplanes have different handles\n"); + return -EINVAL; + } + if (mode_cmd->modifier[0] != mode_cmd->modifier[1]) { + DRM_DEBUG("y and uv subplanes have different modifiers\n"); + return -EINVAL; + } + if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Yf_TILED && + (mode_cmd->offsets[1] & 0xFFF)) { + DRM_DEBUG("tile-Yf uv offset 0x%x isn't starting on new tile-row\n", + mode_cmd->offsets[1]); + return -EINVAL; + } + if (mode_cmd->modifier[1] == I915_FORMAT_MOD_Y_TILED && + ((mode_cmd->offsets[1] / mode_cmd->pitches[1]) % 4)) { + DRM_DEBUG("tile-Y uv offset 0x%x isn't 4-line aligned\n", + mode_cmd->offsets[1]); + return -EINVAL; + } + break; default: DRM_DEBUG("unsupported pixel format: %s\n", - drm_get_format_name(mode_cmd->pixel_format)); + drm_get_format_name(mode_cmd->pixel_format)); return -EINVAL; } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d50b8cb..62d2a11 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -980,7 +980,7 @@ unsigned int intel_fb_align_height(struct drm_device *dev, void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire, enum fb_op_origin origin); u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, - uint32_t pixel_format); + uint32_t pixel_format, int plane); /* intel_audio.c */ void intel_init_audio(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 797594e..49feae0 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -203,7 +203,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, src_w != crtc_w || src_h != crtc_h); stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], - fb->pixel_format); + fb->pixel_format, 0); scaler_id = to_intel_plane_state(drm_plane->state)->scaler_id;