diff mbox

[14/15] drm/i915: skl nv12 wa - NV12 to RGB switch

Message ID 1441839657-20082-1-git-send-email-chandra.konduru@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Chandra Konduru Sept. 9, 2015, 11 p.m. UTC 
Switching format from NV12 to RGB can result in display underrun
and corruption. This workaround sets bits 15 & 19 to 1 in
CLKGATE_DIS_PSL register to address transition underrun.

v2:
-Move workaround to init clock gating (Ville)

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    8 ++++++++
 drivers/gpu/drm/i915/intel_pm.c |    8 ++++++++
 2 files changed, 16 insertions(+)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d20f235..2e2636d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5366,6 +5366,14 @@  enum skl_disp_power_wells {
 #define CHICKEN_DCPR_1             0x46430
 #define IDLE_WAKEMEM_MASK          (1 << 13)
 
+#define CLKGATE_DIS_PSL_A        0x46520
+#define CLKGATE_DIS_PSL_B        0x46524
+#define CLKGATE_DIS_PSL_C        0x46528
+#define DUPS1_GATING_DIS         (1 << 15)
+#define DUPS2_GATING_DIS         (1 << 19)
+#define DUPS3_GATING_DIS         (1 << 23)
+#define CLKGATE_DIS_PSL(pipe)  _PIPE(pipe, CLKGATE_DIS_PSL_A, CLKGATE_DIS_PSL_B)
+
 /* SKL new cursor registers */
 #define _CUR_BUF_CFG_A				0x7017c
 #define _CUR_BUF_CFG_B				0x7117c
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8a36ab9..9a3deed 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -63,6 +63,14 @@  static void gen9_init_clock_gating(struct drm_device *dev)
 	/* WaDisableKillLogic:bxt,skl */
 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 		   ECOCHK_DIS_TLB);
+
+	/*
+	 * Switching format from NV12 to RGB can result in display underrun
+	 * and corruption. This workaround sets bits 15 & 19 to 1 in
+	 * CLKGATE_DIS_PSL register to address transition underrun.
+	 */
+	I915_WRITE(CLKGATE_DIS_PSL(PIPE_A), DUPS1_GATING_DIS | DUPS2_GATING_DIS);
+	I915_WRITE(CLKGATE_DIS_PSL(PIPE_B), DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 }
 
 static void skl_init_clock_gating(struct drm_device *dev)