From patchwork Wed Sep 9 23:00:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chandra Konduru X-Patchwork-Id: 7149681 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 213E5BEEC1 for ; Wed, 9 Sep 2015 23:02:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 496B620862 for ; Wed, 9 Sep 2015 23:02:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6A83D208BA for ; Wed, 9 Sep 2015 23:02:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 10F8A6E0BF; Wed, 9 Sep 2015 16:02:47 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 5413D6E0BF for ; Wed, 9 Sep 2015 16:02:45 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP; 09 Sep 2015 16:02:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,499,1437462000"; d="scan'208";a="786197085" Received: from cmkondur-desk2.fm.intel.com ([10.19.83.171]) by fmsmga001.fm.intel.com with ESMTP; 09 Sep 2015 16:02:37 -0700 From: Chandra Konduru To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Sep 2015 16:00:57 -0700 Message-Id: <1441839657-20082-1-git-send-email-chandra.konduru@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1441420391-19109-15-git-send-email-chandra.konduru@intel.com> References: <1441420391-19109-15-git-send-email-chandra.konduru@intel.com> Cc: daniel.vetter@intel.com, ville.syrjala@intel.com Subject: [Intel-gfx] [PATCH 14/15] drm/i915: skl nv12 wa - NV12 to RGB switch X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Switching format from NV12 to RGB can result in display underrun and corruption. This workaround sets bits 15 & 19 to 1 in CLKGATE_DIS_PSL register to address transition underrun. v2: -Move workaround to init clock gating (Ville) Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d20f235..2e2636d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5366,6 +5366,14 @@ enum skl_disp_power_wells { #define CHICKEN_DCPR_1 0x46430 #define IDLE_WAKEMEM_MASK (1 << 13) +#define CLKGATE_DIS_PSL_A 0x46520 +#define CLKGATE_DIS_PSL_B 0x46524 +#define CLKGATE_DIS_PSL_C 0x46528 +#define DUPS1_GATING_DIS (1 << 15) +#define DUPS2_GATING_DIS (1 << 19) +#define DUPS3_GATING_DIS (1 << 23) +#define CLKGATE_DIS_PSL(pipe) _PIPE(pipe, CLKGATE_DIS_PSL_A, CLKGATE_DIS_PSL_B) + /* SKL new cursor registers */ #define _CUR_BUF_CFG_A 0x7017c #define _CUR_BUF_CFG_B 0x7117c diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8a36ab9..9a3deed 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -63,6 +63,14 @@ static void gen9_init_clock_gating(struct drm_device *dev) /* WaDisableKillLogic:bxt,skl */ I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | ECOCHK_DIS_TLB); + + /* + * Switching format from NV12 to RGB can result in display underrun + * and corruption. This workaround sets bits 15 & 19 to 1 in + * CLKGATE_DIS_PSL register to address transition underrun. + */ + I915_WRITE(CLKGATE_DIS_PSL(PIPE_A), DUPS1_GATING_DIS | DUPS2_GATING_DIS); + I915_WRITE(CLKGATE_DIS_PSL(PIPE_B), DUPS1_GATING_DIS | DUPS2_GATING_DIS); } static void skl_init_clock_gating(struct drm_device *dev)