From patchwork Thu Sep 10 15:34:22 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 7154831 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6AB039F326 for ; Thu, 10 Sep 2015 15:34:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6CEE02085B for ; Thu, 10 Sep 2015 15:34:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8EF742080A for ; Thu, 10 Sep 2015 15:34:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DCAA26E51D; Thu, 10 Sep 2015 08:34:34 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from gproxy8-pub.mail.unifiedlayer.com (gproxy8-pub.mail.unifiedlayer.com [67.222.33.93]) by gabe.freedesktop.org (Postfix) with SMTP id 542946E51D for ; Thu, 10 Sep 2015 08:34:34 -0700 (PDT) Received: (qmail 26789 invoked by uid 0); 10 Sep 2015 15:34:32 -0000 Received: from unknown (HELO CMOut01) (10.0.90.82) by gproxy8.mail.unifiedlayer.com with SMTP; 10 Sep 2015 15:34:32 -0000 Received: from box514.bluehost.com ([74.220.219.114]) by CMOut01 with id FTaU1r00A2UhLwi01TaX5F; Thu, 10 Sep 2015 09:34:31 -0600 X-Authority-Analysis: v=2.1 cv=EbVbHpWC c=1 sm=1 tr=0 a=9W6Fsu4pMcyimqnCr1W0/w==:117 a=9W6Fsu4pMcyimqnCr1W0/w==:17 a=cNaOj0WVAAAA:8 a=f5113yIGAAAA:8 a=TBVoxVdAAAAA:8 a=GhZ5P8ky69gA:10 a=noBwr2J6l1kA:10 a=ff-B7xzCdYMA:10 a=e5mUnYsNAAAA:8 a=qt1y_Qsm3mV13CiWxvYA:9 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=Message-Id:Date:Subject:To:From; bh=jtMDGnnlXDRfBhTFo54WosRtebgK/4gL6N45h3a1sLQ=; b=KgGvsk81qHKRuYZygX11YRSSqqzxIG/Dc45nOjRogjlaSaLwCripPchy8x2iiHDWXaCHb8GAM3VqsUxhMqLIQ39hkmhRj9XHKZQCAIuas3c8vBXmoBlC7o7P5OkVeLQh; Received: from [67.161.37.189] (port=40588 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1.2:AES128-SHA256:128) (Exim 4.84) (envelope-from ) id 1Za3ro-0002Uk-Ng for intel-gfx@lists.freedesktop.org; Thu, 10 Sep 2015 09:34:28 -0600 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Sep 2015 08:34:22 -0700 Message-Id: <1441899263-12986-1-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.9.1 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH 1/2] drm/i915: workaround bad DSL readout in start of pipe update X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On HSW at least (still testing other platforms, but should be harmless elsewhere), the DSL reg reads back as 0 when read around vblank start time. This ends up confusing the atomic start/end checking code, since it causes the update to appear as if it crossed a frame count boundary. Workaround that by avoiding updates in the first couple of scanlines. In testing, even a delay of a single microsecond is enough to give us a good DSL value again, so the millisecond we'll wait when we hit this case occasionally ought to be plenty. References: https://bugs.freedesktop.org/show_bug.cgi?id=91579 Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_sprite.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index ca7e264..0c2c62f 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -113,8 +113,16 @@ void intel_pipe_update_start(struct intel_crtc *crtc) */ prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); + /* + * On HSW, the DSL reg (0x70000) appears to return 0 if we + * read it right around the start of vblank. So skip past it + * so we don't accidentally end up spanning a vblank frame + * increment, causing the update_end() code to squak at us. + * (We use 2 in the comparison to account for the + * scanline_offset used to correct the DSL readout.) + */ scanline = intel_get_crtc_scanline(crtc); - if (scanline < min || scanline > max) + if (scanline > 2 && (scanline < min || scanline > max)) break; if (timeout <= 0) {