diff mbox

[v2,6/7] drm/i915/guc: Notify coarse power gating configuration to GuC properly

Message ID 1442033276-2191-7-git-send-email-sagar.a.kamble@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

sagar.a.kamble@intel.com Sept. 12, 2015, 4:47 a.m. UTC 
From: Alex Dai <yu.dai@intel.com>

GuC expects two bits for Render and Media domain separately when
driver sends data via host2guc SAMPLE_FORCEWAKE when full coarse power
gating is enabled. Bit 0 is for Render and bit 1 is for Media domain.

Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

Comments

yu.dai@intel.com Sept. 21, 2015, 4:51 p.m. UTC | #1 
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> From: Alex Dai <yu.dai@intel.com>
>
> GuC expects two bits for Render and Media domain separately when
> driver sends data via host2guc SAMPLE_FORCEWAKE when full coarse power
> gating is enabled. Bit 0 is for Render and bit 1 is for Media domain.
>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_guc_submission.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 792d0b9..05d1eff4 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -155,10 +155,17 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
>   				     struct i915_guc_client *client)
>   {
>   	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +	struct drm_device *dev = dev_priv->dev;
>   	u32 data[2];
>   
>   	data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
> -	data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0;
> +
> +	/* Notify GuC about Coarse Power Gating where supported */
> +	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> +                ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> +		data[1] = 0;
> +        else
> +		data[1] = (intel_enable_rc6(dev)) ? 3 : 0;
>   

Please hold off this patch. I plan to squash it into 
http://lists.freedesktop.org/archives/intel-gfx/2015-September/075959.html, 
where we remove the magic code '3' here by defining forcewake domain flags.

Thanks,
Alex
yu.dai@intel.com Sept. 21, 2015, 6:59 p.m. UTC | #2 
This one can be discarded and I will amend a fix to my other patch series.

Thanks,
Alex

On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> From: Alex Dai <yu.dai@intel.com>
>
> GuC expects two bits for Render and Media domain separately when
> driver sends data via host2guc SAMPLE_FORCEWAKE when full coarse power
> gating is enabled. Bit 0 is for Render and bit 1 is for Media domain.
>
> Signed-off-by: Alex Dai <yu.dai@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_guc_submission.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 792d0b9..05d1eff4 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -155,10 +155,17 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
>   				     struct i915_guc_client *client)
>   {
>   	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +	struct drm_device *dev = dev_priv->dev;
>   	u32 data[2];
>   
>   	data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
> -	data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0;
> +
> +	/* Notify GuC about Coarse Power Gating where supported */
> +	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> +                ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> +		data[1] = 0;
> +        else
> +		data[1] = (intel_enable_rc6(dev)) ? 3 : 0;
>   
>   	return host2guc_action(guc, data, 2);
>   }
yu.dai@intel.com Sept. 22, 2015, 10:51 p.m. UTC | #3 
On 09/21/2015 09:51 AM, Yu Dai wrote:
> On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
> > From: Alex Dai <yu.dai@intel.com>
> >
> > GuC expects two bits for Render and Media domain separately when
> > driver sends data via host2guc SAMPLE_FORCEWAKE when full coarse power
> > gating is enabled. Bit 0 is for Render and bit 1 is for Media domain.
> >
> > Signed-off-by: Alex Dai <yu.dai@intel.com>
> > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_guc_submission.c | 9 ++++++++-
> >   1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> > index 792d0b9..05d1eff4 100644
> > --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> > @@ -155,10 +155,17 @@ static int host2guc_sample_forcewake(struct intel_guc *guc,
> >   				     struct i915_guc_client *client)
> >   {
> >   	struct drm_i915_private *dev_priv = guc_to_i915(guc);
> > +	struct drm_device *dev = dev_priv->dev;
> >   	u32 data[2];
> >
> >   	data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
> > -	data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0;
> > +
> > +	/* Notify GuC about Coarse Power Gating where supported */
> > +	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
> > +                ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
> > +		data[1] = 0;
> > +        else
> > +		data[1] = (intel_enable_rc6(dev)) ? 3 : 0;
> >
>
> Please hold off this patch. I plan to squash it into
> http://lists.freedesktop.org/archives/intel-gfx/2015-September/075959.html,
> where we remove the magic code '3' here by defining forcewake domain flags.
>
>

I did not add this w/a checking to my new patch series. 
http://lists.freedesktop.org/archives/intel-gfx/2015-September/076348.html. 
We still need this one. Is it better to add definition like 
HAS_CPG(dev)? So we can use it here and also in gen9_enable_rc6.

Thanks,
Alex
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 792d0b9..05d1eff4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -155,10 +155,17 @@  static int host2guc_sample_forcewake(struct intel_guc *guc,
 				     struct i915_guc_client *client)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	struct drm_device *dev = dev_priv->dev;
 	u32 data[2];
 
 	data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
-	data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0;
+
+	/* Notify GuC about Coarse Power Gating where supported */
+	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
+                ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
+		data[1] = 0;
+        else
+		data[1] = (intel_enable_rc6(dev)) ? 3 : 0;
 
 	return host2guc_action(guc, data, 2);
 }