From patchwork Mon Sep 14 18:19:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Zanoni, Paulo R" X-Patchwork-Id: 7177871 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 740379F314 for ; Mon, 14 Sep 2015 18:20:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9A1B220631 for ; Mon, 14 Sep 2015 18:20:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 97ACE20623 for ; Mon, 14 Sep 2015 18:20:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8EB6B6E25E; Mon, 14 Sep 2015 11:20:24 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 430D26E22C for ; Mon, 14 Sep 2015 11:20:19 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 14 Sep 2015 11:20:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,530,1437462000"; d="scan'208";a="768857496" Received: from sschen-mobl3.amr.corp.intel.com (HELO panetone.amr.corp.intel.com) ([10.252.128.173]) by orsmga001.jf.intel.com with ESMTP; 14 Sep 2015 11:20:14 -0700 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Mon, 14 Sep 2015 15:19:56 -0300 Message-Id: <1442254803-20043-2-git-send-email-paulo.r.zanoni@intel.com> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1442254803-20043-1-git-send-email-paulo.r.zanoni@intel.com> References: <1442254803-20043-1-git-send-email-paulo.r.zanoni@intel.com> Subject: [Intel-gfx] [PATCH 2/9] drm/i915: check for the supported strides on HSW+ FBC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Don't allow FBC for cases where the spec says we can't FBC. v2: - Just WARN_ON() the strides that should have been caught earlier (Daniel) - Make it a new function since I expect this to grow more. v3: - Document which IGT test is exercised by this. v4: - Implement the restrictions for gens 2-6 too (Ville). - Fix off-by-one mistake (Ville). Testcase: igt/kms_frontbuffer_tracking/fbc-badstride Signed-off-by: Paulo Zanoni Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_fbc.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3bf8a9b..8cf2969 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -948,6 +948,7 @@ struct i915_fbc { FBC_CHIP_DEFAULT, /* disabled by default on this chip */ FBC_ROTATION, /* rotation is not supported */ FBC_IN_DBG_MASTER, /* kernel debugger is active */ + FBC_BAD_STRIDE, /* stride is not supported */ } no_fbc_reason; bool (*fbc_enabled)(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 9e42079..db38091 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -480,6 +480,8 @@ const char *intel_no_fbc_reason_str(enum no_fbc_reason reason) return "rotation unsupported"; case FBC_IN_DBG_MASTER: return "Kernel debugger is active"; + case FBC_BAD_STRIDE: + return "framebuffer stride not supported"; default: MISSING_CASE(reason); return "unknown reason"; @@ -671,6 +673,27 @@ static int intel_fbc_setup_cfb(struct drm_i915_private *dev_priv, int size, return intel_fbc_alloc_cfb(dev_priv, size, fb_cpp); } +static bool stride_is_valid(struct drm_i915_private *dev_priv, + unsigned int stride) +{ + /* These should have been caught earlier. */ + WARN_ON(stride < 512); + WARN_ON((stride & (64 - 1)) != 0); + + /* Below are the additional FBC restrictions. */ + + if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) + return stride == 4096 || stride == 8192; + + if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) + return false; + + if (stride > 16384) + return false; + + return true; +} + /** * __intel_fbc_update - enable/disable FBC as needed, unlocked * @dev_priv: i915 device instance @@ -781,6 +804,11 @@ static void __intel_fbc_update(struct drm_i915_private *dev_priv) goto out_disable; } + if (!stride_is_valid(dev_priv, fb->pitches[0])) { + set_no_fbc_reason(dev_priv, FBC_BAD_STRIDE); + goto out_disable; + } + /* If the kernel debugger is active, always disable compression */ if (in_dbg_master()) { set_no_fbc_reason(dev_priv, FBC_IN_DBG_MASTER);