From patchwork Tue Sep 15 13:30:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Micha=C5=82_Winiarski?= X-Patchwork-Id: 7185041 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A546ABEEC1 for ; Tue, 15 Sep 2015 13:30:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B350F20515 for ; Tue, 15 Sep 2015 13:30:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E0DE2206CC for ; Tue, 15 Sep 2015 13:30:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6466A6E956; Tue, 15 Sep 2015 06:30:31 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id E463B6E956 for ; Tue, 15 Sep 2015 06:30:29 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP; 15 Sep 2015 06:30:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,536,1437462000"; d="scan'208";a="645204685" Received: from irsmsx151.ger.corp.intel.com ([163.33.192.59]) by orsmga003.jf.intel.com with ESMTP; 15 Sep 2015 06:30:29 -0700 Received: from mwiniars-desk1.igk.intel.com (172.28.173.140) by IRSMSX151.ger.corp.intel.com (163.33.192.59) with Microsoft SMTP Server id 14.3.224.2; Tue, 15 Sep 2015 14:30:28 +0100 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: Date: Tue, 15 Sep 2015 15:30:16 +0200 Message-ID: <1442323816-4712-2-git-send-email-michal.winiarski@intel.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1442323816-4712-1-git-send-email-michal.winiarski@intel.com> References: <1442323816-4712-1-git-send-email-michal.winiarski@intel.com> MIME-Version: 1.0 X-Originating-IP: [172.28.173.140] Cc: Mika Kuoppala Subject: [Intel-gfx] [PATCH 2/2] drm/i915/gtt: Avoid using addresses in non-canonical form. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to bspec, some parts of HW expect the addresses to be in a canonical form where bits [63:48] == [47]. Lets satisfy the HW by converting the address prior to allocating/clearing the entries in page tables. Cc: Michel Thierry Cc: Mika Kuoppala Signed-off-by: Micha? Winiarski --- drivers/gpu/drm/i915/i915_gem_gtt.c | 13 +++++++------ drivers/gpu/drm/i915/i915_gem_gtt.h | 5 +++++ 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 7ff7239..f25a33f 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -766,6 +766,7 @@ static void gen8_ppgtt_clear_range(struct i915_address_space *vm, } else { uint64_t templ4, pml4e; struct i915_page_directory_pointer *pdp; + start = gen8_canonical_addr(start); gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) { gen8_ppgtt_clear_pte_range(vm, pdp, start, length, @@ -1227,15 +1228,10 @@ static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, uint32_t pdpes = I915_PDPES_PER_PDP(dev); int ret; - /* Wrap is never okay since we can only represent 48b, and we don't - * actually use the other side of the canonical address space. - */ + /* Wrap is never okay */ if (WARN_ON(start + length < start)) return -ENODEV; - if (WARN_ON(start + length > vm->total)) - return -ENODEV; - ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); if (ret) return ret; @@ -1333,6 +1329,8 @@ static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, uint64_t temp, pml4e; int ret = 0; + start = gen8_canonical_addr(start); + /* Do the pml4 allocations first, so we don't need to track the newly * allocated tables below the pdp */ bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4); @@ -1377,6 +1375,9 @@ static int gen8_alloc_va_range(struct i915_address_space *vm, struct i915_hw_ppgtt *ppgtt = container_of(vm, struct i915_hw_ppgtt, base); + if (WARN_ON(start + length > vm->total)) + return -ENODEV; + if (USES_FULL_48BIT_PPGTT(vm->dev)) return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); else diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 8275007..9397387 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -503,6 +503,11 @@ static inline size_t gen8_pte_count(uint64_t address, uint64_t length) return i915_pte_count(address, length, GEN8_PDE_SHIFT); } +static inline uint64_t gen8_canonical_addr(uint64_t address) +{ + return ((int64_t)address << 16) >> 16; +} + static inline dma_addr_t i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) {