From patchwork Wed Sep 16 17:37:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sharma, Shashank" X-Patchwork-Id: 7197681 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 17F60BEEC1 for ; Wed, 16 Sep 2015 17:29:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C470D208AF for ; Wed, 16 Sep 2015 17:29:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6BAA220865 for ; Wed, 16 Sep 2015 17:29:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A759372138; Wed, 16 Sep 2015 10:29:50 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id AA4CE72136; Wed, 16 Sep 2015 10:29:48 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP; 16 Sep 2015 10:29:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,540,1437462000"; d="scan'208";a="562948169" Received: from shashanks-desktop.iind.intel.com ([10.223.26.81]) by FMSMGA003.fm.intel.com with ESMTP; 16 Sep 2015 10:29:46 -0700 From: Shashank Sharma To: matthew.d.roper@intel.com, jim.bish@intel.com, robert.bradford@intel.com, gary.k.smith@intel.com, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Wed, 16 Sep 2015 23:07:18 +0530 Message-Id: <1442425040-32185-22-git-send-email-shashank.sharma@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442425040-32185-1-git-send-email-shashank.sharma@intel.com> References: <1442425040-32185-1-git-send-email-shashank.sharma@intel.com> Cc: annie.j.matheson@intel.com, kausalmalladi@gmail.com, daniel.vetter@intel.com Subject: [Intel-gfx] [PATCH 21/23] drm/i915: BDW: Pipe level Gamma correction X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP BDW/SKL/BXT platforms support various Gamma correction modes which are: 1. Legacy 8-bit mode 2. 10-bit mode 3. 10-bit Split Gamma mode 4. 12-bit mode This patch does the following: 1. Adds the core function to program Gamma correction values for BDW/SKL/BXT platforms 2. Adds Gamma correction macros/defines Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi --- drivers/gpu/drm/i915/i915_reg.h | 17 +- drivers/gpu/drm/i915/intel_color_manager.c | 270 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 15 ++ 3 files changed, 300 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5c7759d..88f4e41 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5634,7 +5634,9 @@ enum skl_disp_power_wells { #define _GAMMA_MODE_A 0x4a480 #define _GAMMA_MODE_B 0x4ac80 -#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) +#define _GAMMA_MODE_C 0x4b480 +#define GAMMA_MODE(pipe) \ + _PIPE3(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B, _GAMMA_MODE_C) #define GAMMA_MODE_MODE_MASK (3 << 0) #define GAMMA_MODE_MODE_8BIT (0 << 0) #define GAMMA_MODE_MODE_10BIT (1 << 0) @@ -8001,6 +8003,17 @@ enum skl_disp_power_wells { #define _PIPE_CSC_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_CSC, PIPEB_CGM_CSC, PIPEC_CGM_CSC)) - +/* BDW gamma correction */ +#define PAL_PREC_INDEX_A 0x4A400 +#define PAL_PREC_INDEX_B 0x4AC00 +#define PAL_PREC_INDEX_C 0x4B400 +#define PAL_PREC_DATA_A 0x4A404 +#define PAL_PREC_DATA_B 0x4AC04 +#define PAL_PREC_DATA_C 0x4B404 + +#define _PREC_PAL_INDEX(pipe) \ + (_PIPE3(pipe, PAL_PREC_INDEX_A, PAL_PREC_INDEX_B, PAL_PREC_INDEX_C)) +#define _PREC_PAL_DATA(pipe) \ + (_PIPE3(pipe, PAL_PREC_DATA_A, PAL_PREC_DATA_B, PAL_PREC_DATA_C)) #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index d33a2be..d935fd8 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -264,6 +264,274 @@ static int chv_set_degamma(struct drm_device *dev, return ret; } +static u32 bdw_write_10bit_gamma_precision(u32 red, u32 green, u32 blue) +{ + u32 word; + u8 blue_int, green_int, red_int; + u16 blue_fract, green_fract, red_fract; + + blue_int = _GAMMA_INT_PART(blue); + if (blue_int > GAMMA_INT_MAX) + blue = BDW_MAX_GAMMA; + + green_int = _GAMMA_INT_PART(green); + if (green_int > GAMMA_INT_MAX) + green = BDW_MAX_GAMMA; + + red_int = _GAMMA_INT_PART(red); + if (red_int > GAMMA_INT_MAX) + red = BDW_MAX_GAMMA; + + blue_fract = _GAMMA_FRACT_PART(blue); + green_fract = _GAMMA_FRACT_PART(green); + red_fract = _GAMMA_FRACT_PART(red); + + blue_fract >>= BDW_10BIT_GAMMA_MSB_SHIFT; + green_fract >>= BDW_10BIT_GAMMA_MSB_SHIFT; + red_fract >>= BDW_10BIT_GAMMA_MSB_SHIFT; + + /* Red (29:20) Green (19:10) and Blue (9:0) */ + word = red_fract; + word <<= BDW_GAMMA_SHIFT; + word = word | green_fract; + word <<= BDW_GAMMA_SHIFT; + word = word | blue_fract; + + return word; +} + +/* Apply unity gamma for gamma reset */ +static void bdw_reset_gamma(struct drm_i915_private *dev_priv, + enum pipe pipe) +{ + u16 count = 0; + u32 val; + u32 pal_prec_data = LGC_PALETTE(pipe); + + DRM_DEBUG_DRIVER("\n"); + + /* Reset the palette for unit gamma */ + while (count < BDW_8BIT_GAMMA_MAX_VALS) { + /* Red (23:16) Green (15:8) and Blue (7:0) */ + val = (count << 16) | (count << 8) | count; + I915_WRITE(pal_prec_data, val); + pal_prec_data += 4; + count++; + } +} + +static int bdw_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, + struct drm_crtc *crtc) +{ + u8 blue_int, green_int, red_int; + u16 blue_fract, green_fract, red_fract; + u16 blue_odd, green_odd, red_odd; + u16 blue_even, green_even, red_even; + + enum pipe pipe; + int count, num_samples; + u32 blue, green, red; + u32 mode, pal_prec_index, pal_prec_data; + u32 index, word; + struct drm_palette *gamma_data; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_r32g32b32 *correction_values = NULL; + + if (!blob) { + DRM_ERROR("Null Blob\n"); + return -EINVAL; + } + + gamma_data = (struct drm_palette *)blob->data; + + if (gamma_data->version != GAMMA_DATA_STRUCT_VERSION) { + DRM_DEBUG_KMS("Invalid Gamma Data struct version\n"); + return -EINVAL; + } + + pipe = to_intel_crtc(crtc)->pipe; + num_samples = gamma_data->num_samples; + + pal_prec_index = _PREC_PAL_INDEX(pipe); + pal_prec_data = _PREC_PAL_DATA(pipe); + + correction_values = (struct drm_r32g32b32 *)&gamma_data->lut; + index = I915_READ(pal_prec_index); + switch (num_samples) { + + case 0: + + /* Disable Gamma functionality on Pipe */ + DRM_DEBUG_DRIVER("Disabling gamma on Pipe %c\n", + pipe_name(pipe)); + bdw_reset_gamma(dev_priv, pipe); + word = GAMMA_MODE_MODE_8BIT; + break; + + case BDW_8BIT_GAMMA_MAX_VALS: + + /* Legacy palette */ + pal_prec_data = LGC_PALETTE(pipe); + + count = 0; + while (count < BDW_8BIT_GAMMA_MAX_VALS) { + blue = correction_values[count].b32; + green = correction_values[count].g32; + red = correction_values[count].r32; + + blue_int = _GAMMA_INT_PART(blue); + if (blue_int > GAMMA_INT_MAX) + blue = BDW_MAX_GAMMA; + green_int = _GAMMA_INT_PART(green); + if (green_int > GAMMA_INT_MAX) + green = BDW_MAX_GAMMA; + red_int = _GAMMA_INT_PART(red); + if (red_int > GAMMA_INT_MAX) + red = BDW_MAX_GAMMA; + + blue_fract = _GAMMA_FRACT_PART(blue); + green_fract = _GAMMA_FRACT_PART(green); + red_fract = _GAMMA_FRACT_PART(red); + + blue_fract >>= BDW_8BIT_GAMMA_MSB_SHIFT; + green_fract >>= BDW_8BIT_GAMMA_MSB_SHIFT; + red_fract >>= BDW_8BIT_GAMMA_MSB_SHIFT; + + /* Red (23:16) Green (15:8) and Blue (7:0) */ + word = red_fract; + word <<= BDW_8BIT_GAMMA_SHIFT; + word = word | green_fract; + word <<= BDW_8BIT_GAMMA_SHIFT; + word = word | blue_fract; + + I915_WRITE(pal_prec_data, word); + pal_prec_data += 4; + + count++; + } + + word = GAMMA_MODE_MODE_8BIT; + break; + + case BDW_SPLITGAMMA_MAX_VALS: + + index |= BDW_INDEX_AUTO_INCREMENT | BDW_INDEX_SPLIT_MODE; + I915_WRITE(pal_prec_index, index); + + count = 0; + while (count < BDW_SPLITGAMMA_MAX_VALS) { + blue = correction_values[count].b32; + green = correction_values[count].g32; + red = correction_values[count].r32; + + word = bdw_write_10bit_gamma_precision(red, + green, blue); + I915_WRITE(pal_prec_data, word); + count++; + } + + word = GAMMA_MODE_MODE_SPLIT; + break; + + case BDW_12BIT_GAMMA_MAX_VALS: + + index |= BDW_INDEX_AUTO_INCREMENT; + index &= ~BDW_INDEX_SPLIT_MODE; + I915_WRITE(pal_prec_index, index); + + count = 0; + while (count < BDW_12BIT_GAMMA_MAX_VALS) { + blue = correction_values[count].b32; + green = correction_values[count].g32; + red = correction_values[count].r32; + + blue_int = _GAMMA_INT_PART(blue); + if (blue_int > GAMMA_INT_MAX) + blue = BDW_MAX_GAMMA; + green_int = _GAMMA_INT_PART(green); + if (green_int > GAMMA_INT_MAX) + green = BDW_MAX_GAMMA; + red_int = _GAMMA_INT_PART(red); + if (red_int > GAMMA_INT_MAX) + red = BDW_MAX_GAMMA; + + blue_fract = _GAMMA_FRACT_PART(blue); + green_fract = _GAMMA_FRACT_PART(green); + red_fract = _GAMMA_FRACT_PART(red); + + /* Odd index */ + if (count % 2 == 0) { + blue_odd = blue_fract >> + BDW_12BIT_GAMMA_ODD_SHIFT; + green_odd = green_fract >> + BDW_12BIT_GAMMA_ODD_SHIFT; + red_odd = red_fract >> + BDW_12BIT_GAMMA_ODD_SHIFT; + + word = red_odd; + word = word << BDW_GAMMA_SHIFT; + word = word | green_odd; + word = word << BDW_GAMMA_SHIFT; + word = word | blue_odd; + } else { + blue_even = blue_fract << + BDW_12BIT_GAMMA_EVEN_SHIFT1 >> + BDW_12BIT_GAMMA_EVEN_SHIFT2; + green_even = green_fract << + BDW_12BIT_GAMMA_EVEN_SHIFT1 >> + BDW_12BIT_GAMMA_EVEN_SHIFT2; + red_even = red_fract << + BDW_12BIT_GAMMA_EVEN_SHIFT1 >> + BDW_12BIT_GAMMA_EVEN_SHIFT2; + + word = red_even; + word = word << BDW_GAMMA_SHIFT; + word = word | green_even; + word = word << BDW_GAMMA_SHIFT; + word = word | blue_even; + } + I915_WRITE(pal_prec_data, word); + count++; + } + + word = GAMMA_MODE_MODE_12BIT; + break; + + case BDW_10BIT_GAMMA_MAX_VALS: + + index |= BDW_INDEX_AUTO_INCREMENT; + index &= ~BDW_INDEX_SPLIT_MODE; + I915_WRITE(pal_prec_index, index); + + count = 0; + while (count < BDW_10BIT_GAMMA_MAX_VALS) { + blue = correction_values[count].b32; + green = correction_values[count].g32; + red = correction_values[count].r32; + + word = bdw_write_10bit_gamma_precision(red, + green, blue); + I915_WRITE(pal_prec_data, word); + count++; + } + + word = GAMMA_MODE_MODE_10BIT; + break; + + default: + DRM_ERROR("Invalid number of samples\n"); + return -EINVAL; + } + + /* Set gamma mode on pipe control reg */ + mode = I915_READ(GAMMA_MODE(pipe)); + mode &= ~GAMMA_MODE_MODE_MASK; + I915_WRITE(GAMMA_MODE(pipe), mode | word); + DRM_DEBUG_DRIVER("Gamma applied on pipe %c\n", + pipe_name(pipe)); + return 0; +} + static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, struct drm_crtc *crtc) { @@ -418,6 +686,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev, /* Gamma correction is platform specific */ if (IS_CHERRYVIEW(dev)) ret = chv_set_gamma(dev, blob, crtc); + else if (IS_BROADWELL(dev) || IS_GEN9(dev)) + ret = bdw_set_gamma(dev, blob, crtc); if (ret) DRM_ERROR("set Gamma correction failed\n"); diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 3687989..17fcf3d 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -43,6 +43,9 @@ #define CHV_GAMMA_SHIFT_GREEN 16 #define BDW_SPLITGAMMA_MAX_VALS 512 +#define BDW_8BIT_GAMMA_MAX_VALS 256 +#define BDW_10BIT_GAMMA_MAX_VALS 1024 +#define BDW_12BIT_GAMMA_MAX_VALS 513 /* Gamma values are u8.24 format */ #define GAMMA_INT_SHIFT 24 @@ -52,6 +55,18 @@ /* Max value for Gamma on CHV */ #define CHV_MAX_GAMMA 0x10000 +/* Gen 9 */ +#define BDW_MAX_GAMMA 0x10000 +#define BDW_10BIT_GAMMA_MSB_SHIFT 6 +#define BDW_GAMMA_SHIFT 10 +#define BDW_INDEX_AUTO_INCREMENT (1 << 15) +#define BDW_INDEX_SPLIT_MODE (1 << 31) +#define BDW_8BIT_GAMMA_MSB_SHIFT 8 +#define BDW_8BIT_GAMMA_SHIFT 8 +#define BDW_12BIT_GAMMA_ODD_SHIFT 6 +#define BDW_12BIT_GAMMA_EVEN_SHIFT1 10 +#define BDW_12BIT_GAMMA_EVEN_SHIFT2 6 + /* DeGamma correction */ #define DEGAMMA_DATA_STRUCT_VERSION 1 #define CHV_DEGAMMA_MSB_SHIFT 2