From patchwork Wed Sep 23 15:52:25 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zanoni, Paulo R" X-Patchwork-Id: 7250851 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C70009F32B for ; Wed, 23 Sep 2015 15:52:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E2C5F20A82 for ; Wed, 23 Sep 2015 15:52:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 5C62020A68 for ; Wed, 23 Sep 2015 15:52:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BAC756EDC3; Wed, 23 Sep 2015 08:52:47 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id A7C646EDC7 for ; Wed, 23 Sep 2015 08:52:44 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP; 23 Sep 2015 08:52:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,577,1437462000"; d="scan'208";a="567021014" Received: from ljroach-mobl1.amr.corp.intel.com (HELO panetone.amr.corp.intel.com) ([10.254.81.188]) by FMSMGA003.fm.intel.com with ESMTP; 23 Sep 2015 08:52:43 -0700 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Wed, 23 Sep 2015 12:52:25 -0300 Message-Id: <1443023547-19896-6-git-send-email-paulo.r.zanoni@intel.com> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1443023547-19896-1-git-send-email-paulo.r.zanoni@intel.com> References: <1443023547-19896-1-git-send-email-paulo.r.zanoni@intel.com> Subject: [Intel-gfx] [PATCH 5/7] drm/i915: fix FBC buffer size checks X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to my experiments, the maximum sizes mentioned in the specification delimit how far in the buffer the hardware tracking can go. And the hardware seems to calculate the size based on the plane address and x/y offsets we specify to it. So adjust the code to do the proper checks. On platforms that do the x/y offset adjustment trick it will be really hard to reproduce a bug, but on the current SKL we can reproduce the bug with igt/kms_frontbuffer_tracking/fbc-farfromfence. With this patch, we'll go from "CRC assertion failure" to "FBC unexpectedly disabled", which is still a failure on the test suite but is not a perceived user bug - you will just not save as much power as you could be if FBC is disabled. Testcase: igt/kms_frontbuffer_tracking/fbc-farfromfence (SKL) Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_fbc.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 0c7b59b..2cc2528 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -758,7 +758,7 @@ static bool pixel_format_is_valid(struct drm_framebuffer *fb) static bool size_is_valid(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; - unsigned int max_w, max_h; + unsigned int tracked_w, tracked_h, max_w, max_h; if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { max_w = 4096; @@ -771,8 +771,10 @@ static bool size_is_valid(struct intel_crtc *crtc) max_h = 1536; } - return crtc->config->pipe_src_w <= max_w && - crtc->config->pipe_src_h <= max_h; + tracked_w = (crtc->base.primary->state->src_w >> 16) + crtc->adjusted_x; + tracked_h = (crtc->base.primary->state->src_h >> 16) + crtc->adjusted_y; + + return tracked_w <= max_w && tracked_h <= max_h; } /**