From patchwork Mon Oct 5 07:01:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 7325121 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E93749F302 for ; Mon, 5 Oct 2015 07:02:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1283B206DE for ; Mon, 5 Oct 2015 07:02:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 1A7C5206D8 for ; Mon, 5 Oct 2015 07:02:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 795906E463; Mon, 5 Oct 2015 00:02:09 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 000C16E463 for ; Mon, 5 Oct 2015 00:02:08 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP; 05 Oct 2015 00:02:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,637,1437462000"; d="scan'208";a="657946658" Received: from linux.intel.com ([10.23.219.25]) by orsmga003.jf.intel.com with ESMTP; 05 Oct 2015 00:02:08 -0700 Received: from localhost (aconselv-mobl3.ger.corp.intel.com [10.252.2.166]) by linux.intel.com (Postfix) with ESMTP id E784E6A4083; Mon, 5 Oct 2015 00:01:11 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Mon, 5 Oct 2015 10:01:21 +0300 Message-Id: <1444028487-6501-10-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1444028487-6501-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1444028487-6501-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH 09/15] drm/i915: Move link training setup code to separate functions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move the setup code for the different phases of link training into functions separate from the training loop. This shouldn't cause any change in behavior, but make the code slightly less hard to read. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_dp_link_training.c | 48 ++++++++++++++++++--------- 1 file changed, 33 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c index 4d2bdc0..c936b9d 100644 --- a/drivers/gpu/drm/i915/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c @@ -104,16 +104,11 @@ intel_dp_update_link_train(struct intel_dp *intel_dp) return ret == intel_dp->lane_count; } -/* Enable corresponding port and start training pattern 1 */ static bool -intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) +setup_clock_recovery(struct intel_dp *intel_dp) { - int i; - uint8_t voltage; - int voltage_tries, loop_tries; uint8_t link_config[2]; uint8_t link_bw, rate_select; - uint8_t link_status[DP_LINK_STATUS_SIZE]; if (intel_dp->prepare_link_retrain) intel_dp->prepare_link_retrain(intel_dp); @@ -145,6 +140,21 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) return false; } + return true; +} + +/* Enable corresponding port and start training pattern 1 */ +static bool +intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) +{ + int i; + uint8_t voltage; + int voltage_tries, loop_tries; + uint8_t link_status[DP_LINK_STATUS_SIZE]; + + if (!setup_clock_recovery(intel_dp)) + return false; + voltage = 0xff; voltage_tries = 0; loop_tries = 0; @@ -217,10 +227,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) } static bool -intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) +setup_channel_equalization(struct intel_dp *intel_dp) { - bool channel_eq = false; - int tries, cr_tries; uint32_t training_pattern = DP_TRAINING_PATTERN_2; /* @@ -246,6 +254,18 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) return false; } + return true; +} + +static bool +intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) +{ + bool channel_eq = false; + int tries, cr_tries; + + if (!setup_channel_equalization(intel_dp)) + return false; + tries = 0; cr_tries = 0; channel_eq = false; @@ -268,9 +288,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) intel_dp->lane_count)) { intel_dp->train_set_valid = false; intel_dp_link_training_clock_recovery(intel_dp); - intel_dp_set_link_train(intel_dp, - training_pattern | - DP_LINK_SCRAMBLING_DISABLE); + if (!setup_channel_equalization(intel_dp)) + return false; cr_tries++; continue; } @@ -285,9 +304,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) if (tries > 5) { intel_dp->train_set_valid = false; intel_dp_link_training_clock_recovery(intel_dp); - intel_dp_set_link_train(intel_dp, - training_pattern | - DP_LINK_SCRAMBLING_DISABLE); + if (!setup_channel_equalization(intel_dp)) + return false; tries = 0; cr_tries++; continue;