| Message ID | 1444056277-27679-2-git-send-email-ander.conselvan.de.oliveira@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Please ignore these two patches. They contain errors and are superseded by a new patch series I just sent. Ander On Mon, 2015-10-05 at 17:44 +0300, Ander Conselvan de Oliveira wrote: > Simplify intel_dp_pre_emphasis_max() by grouping the conditions for VLV, > HSW, BDW and gen 9 together, since they all use the same values. > > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 29 ++--------------------------- > 1 file changed, 2 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 3fa8a55..c7f93c5 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -3085,7 +3085,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) > struct drm_device *dev = intel_dp_to_dev(intel_dp); > enum port port = dp_to_dig_port(intel_dp)->port; > > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_INFO(dev)->gen >= 7 || !IS_IVYBRIDGE(dev)) { > switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { > case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: > return DP_TRAIN_PRE_EMPH_LEVEL_3; > @@ -3094,35 +3094,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t > voltage_swing) > case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: > return DP_TRAIN_PRE_EMPH_LEVEL_1; > case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: > - return DP_TRAIN_PRE_EMPH_LEVEL_0; > default: > return DP_TRAIN_PRE_EMPH_LEVEL_0; > } > - } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { > - switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: > - return DP_TRAIN_PRE_EMPH_LEVEL_3; > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: > - return DP_TRAIN_PRE_EMPH_LEVEL_2; > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: > - return DP_TRAIN_PRE_EMPH_LEVEL_1; > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: > - default: > - return DP_TRAIN_PRE_EMPH_LEVEL_0; > - } > - } else if (IS_VALLEYVIEW(dev)) { > - switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: > - return DP_TRAIN_PRE_EMPH_LEVEL_3; > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: > - return DP_TRAIN_PRE_EMPH_LEVEL_2; > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: > - return DP_TRAIN_PRE_EMPH_LEVEL_1; > - case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: > - default: > - return DP_TRAIN_PRE_EMPH_LEVEL_0; > - } > - } else if (IS_GEN7(dev) && port == PORT_A) { > + } else if (IS_IVYBRIDGE(dev) && port == PORT_A) { > switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { > case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: > return DP_TRAIN_PRE_EMPH_LEVEL_2;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3fa8a55..c7f93c5 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3085,7 +3085,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) struct drm_device *dev = intel_dp_to_dev(intel_dp); enum port port = dp_to_dig_port(intel_dp)->port; - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_INFO(dev)->gen >= 7 || !IS_IVYBRIDGE(dev)) { switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: return DP_TRAIN_PRE_EMPH_LEVEL_3; @@ -3094,35 +3094,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: return DP_TRAIN_PRE_EMPH_LEVEL_1; case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: - return DP_TRAIN_PRE_EMPH_LEVEL_0; default: return DP_TRAIN_PRE_EMPH_LEVEL_0; } - } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { - switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: - return DP_TRAIN_PRE_EMPH_LEVEL_3; - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: - return DP_TRAIN_PRE_EMPH_LEVEL_2; - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: - return DP_TRAIN_PRE_EMPH_LEVEL_1; - case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: - default: - return DP_TRAIN_PRE_EMPH_LEVEL_0; - } - } else if (IS_VALLEYVIEW(dev)) { - switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: - return DP_TRAIN_PRE_EMPH_LEVEL_3; - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: - return DP_TRAIN_PRE_EMPH_LEVEL_2; - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: - return DP_TRAIN_PRE_EMPH_LEVEL_1; - case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: - default: - return DP_TRAIN_PRE_EMPH_LEVEL_0; - } - } else if (IS_GEN7(dev) && port == PORT_A) { + } else if (IS_IVYBRIDGE(dev) && port == PORT_A) { switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: return DP_TRAIN_PRE_EMPH_LEVEL_2;
Simplify intel_dp_pre_emphasis_max() by grouping the conditions for VLV, HSW, BDW and gen 9 together, since they all use the same values. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 29 ++--------------------------- 1 file changed, 2 insertions(+), 27 deletions(-)