From patchwork Thu Oct 8 04:28:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Kumar, Shobhit" X-Patchwork-Id: 7348591 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2434ABEEA4 for ; Thu, 8 Oct 2015 04:29:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 28BA4207A6 for ; Thu, 8 Oct 2015 04:29:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id DFA9B20798 for ; Thu, 8 Oct 2015 04:29:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1860D7209D; Wed, 7 Oct 2015 21:29:03 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E61D7209D for ; Wed, 7 Oct 2015 21:29:02 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP; 07 Oct 2015 21:29:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,652,1437462000"; d="scan'208";a="787257217" Received: from skumar40-mobl.iind.intel.com ([10.223.178.193]) by orsmga001.jf.intel.com with ESMTP; 07 Oct 2015 21:29:00 -0700 From: Shobhit Kumar To: intel-gfx@lists.freedesktop.org Date: Thu, 8 Oct 2015 09:58:55 +0530 Message-Id: <1444278535-16483-1-git-send-email-shobhit.kumar@intel.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1444058564-13663-1-git-send-email-shobhit.kumar@intel.com> References: <1444058564-13663-1-git-send-email-shobhit.kumar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [v2] drm/i915/skl: Init cdclk in the driver rather than relying on pre-os X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Reuse what is programmed by pre-os, but in case there is no pre-os initialization, init the cdclk with the max value by default untill dynamic cdclk support comes. v2: Check if BIOS programmed correctly rather than always calling init - Do validation of programmed cdctl and what it is expected - Only do slk_init_cdclk if validation failed else reuse BIOS programmed value Cc: Imre Deak Cc: Ville Syrjälä Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++++++----- drivers/gpu/drm/i915/intel_display.c | 39 +++++++++++++++++++++++++++--------- 2 files changed, 42 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 2d3cc82..3ec5618 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2946,11 +2946,19 @@ void intel_ddi_pll_init(struct drm_device *dev) int cdclk_freq; cdclk_freq = dev_priv->display.get_display_clock_speed(dev); - dev_priv->skl_boot_cdclk = cdclk_freq; - if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) - DRM_ERROR("LCPLL1 is disabled\n"); - else - intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); + + /* Invalid CDCLK from BIOS ? */ + if (cdclk_freq < 0) { + /* program to maximum cdclk till we have dynamic cdclk support */ + dev_priv->skl_boot_cdclk = 675000; + skl_init_cdclk(dev_priv); + } else { + dev_priv->skl_boot_cdclk = cdclk_freq; + if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) + DRM_ERROR("LCPLL1 is disabled\n"); + else + intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); + } } else if (IS_BROXTON(dev)) { broxton_init_cdclk(dev); broxton_ddi_phy_init(dev); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index bbeb6d3..f734410 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6634,12 +6634,15 @@ static int skylake_get_display_clock_speed(struct drm_device *dev) uint32_t lcpll1 = I915_READ(LCPLL1_CTL); uint32_t cdctl = I915_READ(CDCLK_CTL); uint32_t linkrate; + int freq; if (!(lcpll1 & LCPLL_PLL_ENABLE)) return 24000; /* 24MHz is the cd freq with NSSC ref */ - if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) - return 540000; + if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) { + freq = 540000; + goto verify; + } linkrate = (I915_READ(DPLL_CTRL1) & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; @@ -6649,30 +6652,46 @@ static int skylake_get_display_clock_speed(struct drm_device *dev) /* vco 8640 */ switch (cdctl & CDCLK_FREQ_SEL_MASK) { case CDCLK_FREQ_450_432: - return 432000; + freq = 432000; + break; case CDCLK_FREQ_337_308: - return 308570; + freq = 308570; + break; case CDCLK_FREQ_675_617: - return 617140; + freq = 617140; + break; default: WARN(1, "Unknown cd freq selection\n"); + return -EINVAL; } } else { /* vco 8100 */ switch (cdctl & CDCLK_FREQ_SEL_MASK) { case CDCLK_FREQ_450_432: - return 450000; + freq = 450000; + break; case CDCLK_FREQ_337_308: - return 337500; + freq = 337500; + break; case CDCLK_FREQ_675_617: - return 675000; + freq = 675000; + break; default: WARN(1, "Unknown cd freq selection\n"); + return -EINVAL; } } - /* error case, do as if DPLL0 isn't enabled */ - return 24000; +verify: + /* + * Noticed in some instances that the freq selection is correct but + * decimal part is programmed wrong from BIOS where pre-os does not + * enable display. Verify the same as well. + */ + if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) + return freq; + else + return -EINVAL; } static int broxton_get_display_clock_speed(struct drm_device *dev)