From patchwork Tue Oct 13 12:39:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sharma, Shashank" X-Patchwork-Id: 7384631 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9D4FF9F1D5 for ; Tue, 13 Oct 2015 12:32:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5806D20962 for ; Tue, 13 Oct 2015 12:32:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 44BFF2053F for ; Tue, 13 Oct 2015 12:32:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D3A67A14E; Tue, 13 Oct 2015 05:32:44 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 090A17A150; Tue, 13 Oct 2015 05:32:42 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 13 Oct 2015 05:32:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,678,1437462000"; d="scan'208";a="825801973" Received: from shashanks-desktop.iind.intel.com ([10.223.26.81]) by fmsmga002.fm.intel.com with ESMTP; 13 Oct 2015 05:31:45 -0700 From: Shashank Sharma To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, emil.l.velikov@gmail.com, matthew.d.roper@intel.com, robert.bradford@intel.com, jim.bish@intel.com Date: Tue, 13 Oct 2015 18:09:48 +0530 Message-Id: <1444739997-24831-14-git-send-email-shashank.sharma@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444739997-24831-1-git-send-email-shashank.sharma@intel.com> References: <1444739997-24831-1-git-send-email-shashank.sharma@intel.com> Cc: annie.j.matheson@intel.com, kausalmalladi@gmail.com, daniel.vetter@intel.com, =gary.k.smith@intel.com Subject: [Intel-gfx] [PATCH v5 13/22] drm/i915: CHV: Pipe level Gamma correction X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP CHV/BSW platform supports two different pipe level gamma correction modes, which are: 1. Legacy 8-bit mode 2. 10-bit CGM (Color Gamut Mapping) mode This patch does the following: 1. Attaches Gamma property to CRTC 3. Adds the core Gamma correction function for CHV/BSW 4. Adds Gamma correction macros Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi --- drivers/gpu/drm/i915/i915_reg.h | 12 ++++ drivers/gpu/drm/i915/intel_color_manager.c | 96 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 13 ++++ 3 files changed, 121 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 88b3da2..8e0a1b1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8148,4 +8148,16 @@ enum skl_disp_power_wells { #define GEN9_VEBOX_MOCS_0 0xcb00 /* Video MOCS base register*/ #define GEN9_BLT_MOCS_0 0xcc00 /* Blitter MOCS base register*/ +/* Color Management */ +#define PIPEA_CGM_CONTROL (VLV_DISPLAY_BASE + 0x67A00) +#define PIPEB_CGM_CONTROL (VLV_DISPLAY_BASE + 0x69A00) +#define PIPEC_CGM_CONTROL (VLV_DISPLAY_BASE + 0x6BA00) +#define PIPEA_CGM_GAMMA (VLV_DISPLAY_BASE + 0x67000) +#define PIPEB_CGM_GAMMA (VLV_DISPLAY_BASE + 0x69000) +#define PIPEC_CGM_GAMMA (VLV_DISPLAY_BASE + 0x6B000) +#define _PIPE_CGM_CONTROL(pipe) \ + (_PIPE3(pipe, PIPEA_CGM_CONTROL, PIPEB_CGM_CONTROL, PIPEC_CGM_CONTROL)) +#define _PIPE_GAMMA_BASE(pipe) \ + (_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA)) + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index e466748..498e048 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,94 @@ #include "intel_color_manager.h" +static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, + struct drm_crtc *crtc) +{ + enum pipe pipe; + u16 red_fract, green_fract, blue_fract; + u32 red, green, blue, num_samples; + u32 word = 0; + u32 count, cgm_gamma_reg, cgm_control_reg; + u64 length; + struct drm_r32g32b32 *correction_values; + struct drm_palette *gamma_data; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_crtc_state *state = crtc->state; + + if (WARN_ON(!blob)) + return -EINVAL; + + gamma_data = (struct drm_palette *)blob->data; + pipe = to_intel_crtc(crtc)->pipe; + num_samples = gamma_data->num_samples; + length = num_samples * sizeof(struct drm_r32g32b32); + + switch (num_samples) { + case GAMMA_DISABLE_VALS: + + /* Disable Gamma functionality on Pipe - CGM Block */ + cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe)); + cgm_control_reg &= ~CGM_GAMMA_EN; + I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg); + state->palette_after_ctm_blob = NULL; + DRM_DEBUG_DRIVER("Gamma disabled on Pipe %c\n", + pipe_name(pipe)); + return 0; + + case CHV_8BIT_GAMMA_MAX_VALS: + case CHV_10BIT_GAMMA_MAX_VALS: + + count = 0; + cgm_gamma_reg = _PIPE_GAMMA_BASE(pipe); + correction_values = gamma_data->lut; + + while (count < num_samples) { + blue = correction_values[count].b32; + green = correction_values[count].g32; + red = correction_values[count].r32; + + if (blue > CHV_MAX_GAMMA) + blue = CHV_MAX_GAMMA; + + if (green > CHV_MAX_GAMMA) + green = CHV_MAX_GAMMA; + + if (red > CHV_MAX_GAMMA) + red = CHV_MAX_GAMMA; + + /* get MSB 10 bits from fraction part (14:23) */ + blue_fract = GET_BITS(blue, 14, 10); + green_fract = GET_BITS(green, 14, 10); + red_fract = GET_BITS(red, 14, 10); + + /* Green (25:16) and Blue (9:0) to be written */ + SET_BITS(word, green_fract, 16, 10); + SET_BITS(word, blue_fract, 0, 10); + I915_WRITE(cgm_gamma_reg, word); + cgm_gamma_reg += 4; + + /* Red (9:0) to be written */ + word = red_fract; + I915_WRITE(cgm_gamma_reg, word); + + cgm_gamma_reg += 4; + count++; + } + + /* Enable (CGM) Gamma on Pipe */ + I915_WRITE(_PIPE_CGM_CONTROL(pipe), + I915_READ(_PIPE_CGM_CONTROL(pipe)) | CGM_GAMMA_EN); + DRM_DEBUG_DRIVER("CGM Gamma enabled on Pipe %c\n", + pipe_name(pipe)); + return 0; + + default: + DRM_ERROR("Invalid number of samples (%u) for Gamma LUT\n", + num_samples); + return -EINVAL; + } +} + void intel_attach_color_properties_to_crtc(struct drm_device *dev, struct drm_crtc *crtc) { @@ -61,4 +149,12 @@ void intel_attach_color_properties_to_crtc(struct drm_device *dev, INTEL_INFO(dev)->num_samples_before_ctm); DRM_DEBUG_DRIVER("Degamma query property initialized\n"); } + + /* Gamma correction */ + if (config->cm_palette_after_ctm_property) { + drm_object_attach_property(mode_obj, + config->cm_palette_after_ctm_property, 0); + DRM_DEBUG_DRIVER("gamma property attached to CRTC\n"); + } + } diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 14a1309..de706d9 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -52,3 +52,16 @@ /* CHV */ #define CHV_10BIT_GAMMA_MAX_VALS 257 #define CHV_DEGAMMA_MAX_VALS 65 + +/* No of coeff for disabling gamma is 0 */ +#define GAMMA_DISABLE_VALS 0 + +/* Gamma on CHV */ +#define CHV_10BIT_GAMMA_MAX_VALS 257 +#define CHV_8BIT_GAMMA_MAX_VALS 256 +#define CHV_10BIT_GAMMA_MSB_SHIFT 6 +#define CHV_GAMMA_SHIFT_GREEN 16 +#define CHV_MAX_GAMMA ((1 << 24) - 1) + +/* CHV CGM Block */ +#define CGM_GAMMA_EN (1 << 2)