From patchwork Tue Oct 13 12:39:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sharma, Shashank" X-Patchwork-Id: 7384761 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0E0C8BFD59 for ; Tue, 13 Oct 2015 12:33:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 17AF7209AA for ; Tue, 13 Oct 2015 12:33:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E873D209A9 for ; Tue, 13 Oct 2015 12:32:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 815BA7A162; Tue, 13 Oct 2015 05:32:57 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 7AEC17A15E; Tue, 13 Oct 2015 05:32:55 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 13 Oct 2015 05:32:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,678,1437462000"; d="scan'208";a="825802122" Received: from shashanks-desktop.iind.intel.com ([10.223.26.81]) by fmsmga002.fm.intel.com with ESMTP; 13 Oct 2015 05:32:16 -0700 From: Shashank Sharma To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, emil.l.velikov@gmail.com, matthew.d.roper@intel.com, robert.bradford@intel.com, jim.bish@intel.com Date: Tue, 13 Oct 2015 18:09:55 +0530 Message-Id: <1444739997-24831-21-git-send-email-shashank.sharma@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444739997-24831-1-git-send-email-shashank.sharma@intel.com> References: <1444739997-24831-1-git-send-email-shashank.sharma@intel.com> Cc: annie.j.matheson@intel.com, kausalmalladi@gmail.com, daniel.vetter@intel.com, =gary.k.smith@intel.com Subject: [Intel-gfx] [PATCH v5 20/22] drm/i915: BDW: Load degamma correction values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP I915 color manager registers pipe degamma correction as palette correction before CTM, DRM property. This patch adds the no of coefficients(512) for degamma correction as "num_samples_before_ctm" parameter in device info structures, for BDW and higher platforms. Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi --- drivers/gpu/drm/i915/i915_drv.c | 7 +++++++ drivers/gpu/drm/i915/intel_color_manager.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 8beac5c..1c68e91 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -303,6 +303,7 @@ static const struct intel_device_info intel_broadwell_d_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -316,6 +317,7 @@ static const struct intel_device_info intel_broadwell_m_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -329,6 +331,7 @@ static const struct intel_device_info intel_broadwell_gt3d_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -342,6 +345,7 @@ static const struct intel_device_info intel_broadwell_gt3m_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -368,6 +372,7 @@ static const struct intel_device_info intel_skylake_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -382,6 +387,7 @@ static const struct intel_device_info intel_skylake_gt3_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -396,6 +402,7 @@ static const struct intel_device_info intel_broxton_info = { .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, + .num_samples_before_ctm = BDW_DEGAMMA_MAX_VALS, .num_pipes = 3, .has_ddi = 1, .has_fpga_dbg = 1, diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 6c7cb08..e0c486e 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -98,3 +98,6 @@ #define BDW_MAX_GAMMA ((1 << 24) - 1) #define BDW_INDEX_AUTO_INCREMENT (1 << 15) #define BDW_INDEX_SPLIT_MODE (1 << 31) + +/* Degamma on BDW */ +#define BDW_DEGAMMA_MAX_VALS 512