@@ -9738,6 +9738,17 @@ static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
}
}
+void intel_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+ struct intel_crtc_state *pipe_config)
+{
+ if (IS_SKYLAKE(dev_priv))
+ skylake_get_ddi_pll(dev_priv, port, pipe_config);
+ else if (IS_BROXTON(dev_priv))
+ bxt_get_ddi_pll(dev_priv, port, pipe_config);
+ else
+ haswell_get_ddi_pll(dev_priv, port, pipe_config);
+}
+
static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
@@ -9751,12 +9762,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
- if (IS_SKYLAKE(dev))
- skylake_get_ddi_pll(dev_priv, port, pipe_config);
- else if (IS_BROXTON(dev))
- bxt_get_ddi_pll(dev_priv, port, pipe_config);
- else
- haswell_get_ddi_pll(dev_priv, port, pipe_config);
+ intel_get_ddi_pll(dev_priv, port, pipe_config);
if (pipe_config->shared_dpll >= 0) {
pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
@@ -991,6 +991,8 @@ void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
bool intel_ddi_pll_select(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder, bool find_dpll);
+void intel_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+ struct intel_crtc_state *pipe_config);
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
This patch wraps the get_ddi_pll() methods for SKL/BXT/HSW+ with a common intel_get_ddi_pll() method, and exports it, so that it can be shared by other users also. Signed-off-by: Durgadoss R <durgadoss.r@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++------ drivers/gpu/drm/i915/intel_drv.h | 2 ++ 2 files changed, 14 insertions(+), 6 deletions(-)