From patchwork Thu Oct 15 13:22:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vandana.kannan@intel.com X-Patchwork-Id: 7405901 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 00AED9F6E4 for ; Thu, 15 Oct 2015 12:55:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0CAEB20841 for ; Thu, 15 Oct 2015 12:55:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 0E6FB20839 for ; Thu, 15 Oct 2015 12:55:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 744816EE78; Thu, 15 Oct 2015 05:55:01 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id C02FE6EE78 for ; Thu, 15 Oct 2015 05:54:59 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP; 15 Oct 2015 05:54:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,685,1437462000"; d="scan'208";a="827345681" Received: from vkannan-desktop.iind.intel.com ([10.223.25.49]) by orsmga002.jf.intel.com with ESMTP; 15 Oct 2015 05:54:59 -0700 From: Vandana Kannan To: intel-gfx@lists.freedesktop.org Date: Thu, 15 Oct 2015 18:52:48 +0530 Message-Id: <1444915369-32134-2-git-send-email-vandana.kannan@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444915369-32134-1-git-send-email-vandana.kannan@intel.com> References: <1444915369-32134-1-git-send-email-vandana.kannan@intel.com> Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Create crtc_clock_get function pointers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There are separate functions i9xx_crtc_clock_get(), vlv_crtc_clock_get(), chv_crtc_clock_get(). instead of calling these using if-else, making func pointers. This will also be useful going forward when the implementation for BXT is done. Signed-off-by: Vandana Kannan --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++-------- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 8afda45..773f507 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -607,6 +607,8 @@ struct intel_limit; struct dpll; struct drm_i915_display_funcs { + void (*crtc_clock_get)(struct intel_crtc *crtc, + struct intel_crtc_state *pipe_config); int (*get_display_clock_speed)(struct drm_device *dev); int (*get_fifo_size)(struct drm_device *dev, int plane); /** diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c28fb6a..d98385e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8130,12 +8130,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, DPLL_PORTB_READY_MASK); } - if (IS_CHERRYVIEW(dev)) - chv_crtc_clock_get(crtc, pipe_config); - else if (IS_VALLEYVIEW(dev)) - vlv_crtc_clock_get(crtc, pipe_config); - else - i9xx_crtc_clock_get(crtc, pipe_config); + dev_priv->display.crtc_clock_get(crtc, pipe_config); /* * Normally the dotclock is filled in by the encoder .get_config() @@ -10579,9 +10574,10 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; /* read out port_clock from the DPLL */ - i9xx_crtc_clock_get(crtc, pipe_config); + dev_priv->display.crtc_clock_get(crtc, &pipe_config); /* * This value does not include pixel_multiplier. @@ -10625,7 +10621,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); - i9xx_crtc_clock_get(intel_crtc, &pipe_config); + dev_priv->display.crtc_clock_get(intel_crtc, &pipe_config); mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; mode->hdisplay = (htot & 0xffff) + 1; @@ -14413,6 +14409,7 @@ static void intel_init_display(struct drm_device *dev) dev_priv->display.crtc_disable = haswell_crtc_disable; dev_priv->display.update_primary_plane = skylake_update_primary_plane; + dev_priv->display.crtc_clock_get = i9xx_crtc_clock_get; } else if (HAS_DDI(dev)) { dev_priv->display.get_pipe_config = haswell_get_pipe_config; dev_priv->display.get_initial_plane_config = @@ -14423,6 +14420,7 @@ static void intel_init_display(struct drm_device *dev) dev_priv->display.crtc_disable = haswell_crtc_disable; dev_priv->display.update_primary_plane = ironlake_update_primary_plane; + dev_priv->display.crtc_clock_get = i9xx_crtc_clock_get; } else if (HAS_PCH_SPLIT(dev)) { dev_priv->display.get_pipe_config = ironlake_get_pipe_config; dev_priv->display.get_initial_plane_config = @@ -14433,6 +14431,7 @@ static void intel_init_display(struct drm_device *dev) dev_priv->display.crtc_disable = ironlake_crtc_disable; dev_priv->display.update_primary_plane = ironlake_update_primary_plane; + dev_priv->display.crtc_clock_get = i9xx_crtc_clock_get; } else if (IS_VALLEYVIEW(dev)) { dev_priv->display.get_pipe_config = i9xx_get_pipe_config; dev_priv->display.get_initial_plane_config = @@ -14442,6 +14441,10 @@ static void intel_init_display(struct drm_device *dev) dev_priv->display.crtc_disable = i9xx_crtc_disable; dev_priv->display.update_primary_plane = i9xx_update_primary_plane; + if (IS_CHERRYVIEW(dev)) + dev_priv->display.crtc_clock_get = chv_crtc_clock_get; + else + dev_priv->display.crtc_clock_get = vlv_crtc_clock_get; } else { dev_priv->display.get_pipe_config = i9xx_get_pipe_config; dev_priv->display.get_initial_plane_config = @@ -14451,6 +14454,7 @@ static void intel_init_display(struct drm_device *dev) dev_priv->display.crtc_disable = i9xx_crtc_disable; dev_priv->display.update_primary_plane = i9xx_update_primary_plane; + dev_priv->display.crtc_clock_get = i9xx_crtc_clock_get; } /* Returns the core display clock speed */