From patchwork Fri Oct 23 10:01:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 7471411 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8F132BF90C for ; Fri, 23 Oct 2015 10:02:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5B12320867 for ; Fri, 23 Oct 2015 10:02:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id BA9DB206E3 for ; Fri, 23 Oct 2015 10:02:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 146FC6E31A; Fri, 23 Oct 2015 03:02:37 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 06D586E421 for ; Fri, 23 Oct 2015 03:02:35 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 23 Oct 2015 03:02:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,186,1444719600"; d="scan'208";a="833325278" Received: from linux.intel.com ([10.23.219.25]) by orsmga002.jf.intel.com with ESMTP; 23 Oct 2015 03:02:35 -0700 Received: from localhost (aconselv-mobl3.ger.corp.intel.com [10.252.19.216]) by linux.intel.com (Postfix) with ESMTP id 02D656A4083; Fri, 23 Oct 2015 03:01:34 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org, jim.bride@linux.intel.com, sivakumar.thulasimani@intel.com Date: Fri, 23 Oct 2015 13:01:54 +0300 Message-Id: <1445594525-7174-12-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1445594525-7174-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1445594525-7174-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH 11/22] drm/i915: Split full retries loop out of clock recovery code (v2) X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When a failure to achieve clock recovery happens, the link training code repeats the training process starting with initial values up to five times before giving up. The logic for the so called "full retries" and the "voltage tries" was convoluted into a single loop. This patch splits it into two separate loops, making it easier to follow. Note that prior to this patch, a failure to get clock recovery with previously know good values wouldn't count as a voltage or full retry failure, but now that counts as a full retry failure. v2: Rebase Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_dp_link_training.c | 79 +++++++++++++-------------- 1 file changed, 37 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c index e5b9410..9f47d8e 100644 --- a/drivers/gpu/drm/i915/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c @@ -132,14 +132,6 @@ setup_clock_recovery(struct intel_dp *intel_dp) intel_dp->DP |= DP_PORT_EN; - /* clock recovery */ - if (!intel_dp_reset_link_train(intel_dp, - DP_TRAINING_PATTERN_1 | - DP_LINK_SCRAMBLING_DISABLE)) { - DRM_ERROR("failed to enable link training\n"); - return false; - } - return true; } @@ -161,19 +153,12 @@ intel_dp_get_train_voltage(struct intel_dp *intel_dp) return intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; } -/* Enable corresponding port and start training pattern 1 */ -static void -intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) +static bool +clock_recovery_voltage_step(struct intel_dp *intel_dp) { - uint8_t voltage; - int voltage_tries, loop_tries; - - if (!setup_clock_recovery(intel_dp)) - return; + int voltage_tries = 0; + uint8_t voltage = 0xff; - voltage = 0xff; - voltage_tries = 0; - loop_tries = 0; for (;;) { uint8_t link_status[DP_LINK_STATUS_SIZE]; @@ -183,10 +168,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) break; } - if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { - DRM_DEBUG_KMS("clock recovery OK\n"); - break; - } + if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) + return true; /* * if we used previously trained voltage and pre-emphasis values @@ -196,28 +179,12 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) DRM_DEBUG_KMS("clock recovery not ok, reset"); /* clear the flag as we are not reusing train set */ intel_dp->train_set_valid = false; - if (!intel_dp_reset_link_train(intel_dp, - DP_TRAINING_PATTERN_1 | - DP_LINK_SCRAMBLING_DISABLE)) { - DRM_ERROR("failed to enable link training\n"); - return; - } - continue; + break; } /* Check to see if we've tried the max voltage */ - if (max_voltage_reached_on_all_lanes(intel_dp)) { - ++loop_tries; - if (loop_tries == 5) { - DRM_ERROR("too many full retries, give up\n"); - break; - } - intel_dp_reset_link_train(intel_dp, - DP_TRAINING_PATTERN_1 | - DP_LINK_SCRAMBLING_DISABLE); - voltage_tries = 0; - continue; - } + if (max_voltage_reached_on_all_lanes(intel_dp)) + break; /* Check to see if we've tried the same voltage 5 times */ if (intel_dp_get_train_voltage(intel_dp) == voltage) { @@ -237,6 +204,34 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) break; } } + + return false; +} + +/* Enable corresponding port and start training pattern 1 */ +static void +intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) +{ + int loop_tries; + + if (!setup_clock_recovery(intel_dp)) + return; + + for (loop_tries = 0; loop_tries < 5; loop_tries++) { + if (!intel_dp_reset_link_train(intel_dp, + DP_TRAINING_PATTERN_1 | + DP_LINK_SCRAMBLING_DISABLE)) { + DRM_ERROR("failed to enable link training\n"); + return; + } + + if (clock_recovery_voltage_step(intel_dp)) { + DRM_DEBUG_KMS("clock recovery OK\n"); + return; + } + } + + DRM_ERROR("too many full retries, give up\n"); } static bool