From patchwork Fri Oct 23 10:01:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 7471461 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F0E11BEEA4 for ; Fri, 23 Oct 2015 10:02:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C00D020847 for ; Fri, 23 Oct 2015 10:02:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8F9B020667 for ; Fri, 23 Oct 2015 10:02:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EB37C721C4; Fri, 23 Oct 2015 03:02:51 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 19711721CD for ; Fri, 23 Oct 2015 03:02:49 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP; 23 Oct 2015 03:02:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,186,1444719600"; d="scan'208";a="833325389" Received: from linux.intel.com ([10.23.219.25]) by orsmga002.jf.intel.com with ESMTP; 23 Oct 2015 03:02:49 -0700 Received: from localhost (aconselv-mobl3.ger.corp.intel.com [10.252.19.216]) by linux.intel.com (Postfix) with ESMTP id 34ED46A4087; Fri, 23 Oct 2015 03:01:47 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org, jim.bride@linux.intel.com, sivakumar.thulasimani@intel.com Date: Fri, 23 Oct 2015 13:01:59 +0300 Message-Id: <1445594525-7174-17-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1445594525-7174-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1445594525-7174-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH 16/22] drm/i915: Introduce struct intel_dp_signal_levels X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In order to clarify which platforms support which combination of voltage swing and pre emphasis level, introduce struct intel_dp_signal_levels. With the new struct, the if ladder to determine the values used is put in one place, intel_dp_init_signal_levels(). This also wires gens 4, 5 and non-eDP ports on gen 6 and 7 to use the new struct. v2: Rebase Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_dp.c | 2 + drivers/gpu/drm/i915/intel_dp_signal_levels.c | 103 ++++++++++++++++++++++---- drivers/gpu/drm/i915/intel_drv.h | 11 +++ 3 files changed, 101 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1236791..e640b59 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5220,6 +5220,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, if (HAS_DDI(dev)) intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; + intel_dp_init_signal_levels(intel_dp); + /* Preserve the current hw state. */ intel_dp->DP = I915_READ(intel_dp->output_reg); intel_dp->attached_connector = intel_connector; diff --git a/drivers/gpu/drm/i915/intel_dp_signal_levels.c b/drivers/gpu/drm/i915/intel_dp_signal_levels.c index e516dd2..365bdc4 100644 --- a/drivers/gpu/drm/i915/intel_dp_signal_levels.c +++ b/drivers/gpu/drm/i915/intel_dp_signal_levels.c @@ -24,8 +24,8 @@ #include "intel_drv.h" /* These are source-specific values. */ -uint8_t -intel_dp_voltage_max(struct intel_dp *intel_dp) +static uint8_t +_dp_voltage_max(struct intel_dp *intel_dp) { struct drm_device *dev = intel_dp_to_dev(intel_dp); struct drm_i915_private *dev_priv = dev->dev_private; @@ -47,8 +47,8 @@ intel_dp_voltage_max(struct intel_dp *intel_dp) return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; } -uint8_t -intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) +static uint8_t +_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) { struct drm_device *dev = intel_dp_to_dev(intel_dp); enum port port = dp_to_dig_port(intel_dp)->port; @@ -389,10 +389,10 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp) return 0; } -static uint32_t -gen4_signal_levels(uint8_t train_set) +static void +gen4_set_signal_levels(struct intel_dp *intel_dp, uint8_t train_set) { - uint32_t signal_levels = 0; + uint32_t signal_levels = 0; switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: @@ -424,9 +424,38 @@ gen4_signal_levels(uint8_t train_set) signal_levels |= DP_PRE_EMPHASIS_9_5; break; } - return signal_levels; + + DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); + + intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK); + intel_dp->DP |= signal_levels; } +static const struct signal_levels gen4_signal_levels = { + .max_voltage = DP_TRAIN_VOLTAGE_SWING_LEVEL_2, + .max_pre_emph = { + DP_TRAIN_PRE_EMPH_LEVEL_2, + DP_TRAIN_PRE_EMPH_LEVEL_2, + DP_TRAIN_PRE_EMPH_LEVEL_1, + DP_TRAIN_PRE_EMPH_LEVEL_0, + }, + + .set = gen4_set_signal_levels, +}; + +/* Not for eDP */ +static const struct signal_levels snb_signal_levels = { + .max_voltage = DP_TRAIN_VOLTAGE_SWING_LEVEL_3, + .max_pre_emph = { + DP_TRAIN_PRE_EMPH_LEVEL_2, + DP_TRAIN_PRE_EMPH_LEVEL_2, + DP_TRAIN_PRE_EMPH_LEVEL_1, + DP_TRAIN_PRE_EMPH_LEVEL_0, + }, + + .set = gen4_set_signal_levels, +}; + /* Gen6's DP voltage swing and pre-emphasis control */ static uint32_t gen6_edp_signal_levels(uint8_t train_set) @@ -486,13 +515,12 @@ gen7_edp_signal_levels(uint8_t train_set) } } -void -intel_dp_set_signal_levels(struct intel_dp *intel_dp) +static void +_update_signal_levels(struct intel_dp *intel_dp) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); enum port port = intel_dig_port->port; struct drm_device *dev = intel_dig_port->base.base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); uint32_t signal_levels, mask = 0; uint8_t train_set = intel_dp->train_set[0]; @@ -514,21 +542,66 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) signal_levels = gen6_edp_signal_levels(train_set); mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; } else { - signal_levels = gen4_signal_levels(train_set); - mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; + WARN(1, "Should be calling intel_dp->signal_levels->set instead."); + return; } if (mask) DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); + intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; +} + +uint8_t +intel_dp_voltage_max(struct intel_dp *intel_dp) +{ + if (intel_dp->signal_levels) + return intel_dp->signal_levels->max_voltage; + else + return _dp_voltage_max(intel_dp); +} + +uint8_t +intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) +{ + if (intel_dp->signal_levels) + return intel_dp->signal_levels->max_pre_emph[voltage_swing]; + else + return _dp_pre_emphasis_max(intel_dp, voltage_swing); +} + +void +intel_dp_set_signal_levels(struct intel_dp *intel_dp) +{ + struct drm_device *dev = intel_dp_to_dev(intel_dp); + struct drm_i915_private *dev_priv = to_i915(dev); + uint8_t train_set = intel_dp->train_set[0]; + + if (intel_dp->signal_levels) + intel_dp->signal_levels->set(intel_dp, train_set); + else + _update_signal_levels(intel_dp); + DRM_DEBUG_KMS("Using vswing level %d\n", train_set & DP_TRAIN_VOLTAGE_SWING_MASK); DRM_DEBUG_KMS("Using pre-emphasis level %d\n", (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT); - intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; - I915_WRITE(intel_dp->output_reg, intel_dp->DP); POSTING_READ(intel_dp->output_reg); } + +void +intel_dp_init_signal_levels(struct intel_dp *intel_dp) +{ + struct drm_device *dev = intel_dp_to_dev(intel_dp); + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + enum port port = intel_dig_port->port; + + if (port != PORT_A && (IS_IVYBRIDGE(dev) || IS_GEN6(dev))) + intel_dp->signal_levels = &snb_signal_levels; + + if (INTEL_INFO(dev)->gen <= 5) + intel_dp->signal_levels = &gen4_signal_levels; +} diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d758e94..e00ce6c 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -726,6 +726,14 @@ struct sink_crc { int last_count; }; +struct intel_dp; +struct signal_levels { + uint8_t max_voltage; + uint8_t max_pre_emph[4]; + + void (*set)(struct intel_dp *intel_dp, uint8_t train_set); +}; + struct intel_dp { uint32_t output_reg; uint32_t aux_ch_ctl_reg; @@ -744,6 +752,7 @@ struct intel_dp { int sink_rates[DP_MAX_SUPPORTED_RATES]; struct sink_crc sink_crc; struct drm_dp_aux aux; + const struct signal_levels *signal_levels; uint8_t train_set[4]; int panel_power_up_delay; int panel_power_down_delay; @@ -1263,6 +1272,8 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); bool intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]); +void intel_dp_init_signal_levels(struct intel_dp *intel_dp); + /* intel_dp_mst.c */ int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);