From patchwork Fri Oct 23 10:02:00 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 7471491 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9E3A29F7C9 for ; Fri, 23 Oct 2015 10:02:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8D7BA20867 for ; Fri, 23 Oct 2015 10:02:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7839F20847 for ; Fri, 23 Oct 2015 10:02:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5713872262; Fri, 23 Oct 2015 03:02:54 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 8D80172262 for ; Fri, 23 Oct 2015 03:02:52 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP; 23 Oct 2015 03:02:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,186,1444719600"; d="scan'208";a="833746766" Received: from linux.intel.com ([10.23.219.25]) by fmsmga002.fm.intel.com with ESMTP; 23 Oct 2015 03:02:52 -0700 Received: from localhost (aconselv-mobl3.ger.corp.intel.com [10.252.19.216]) by linux.intel.com (Postfix) with ESMTP id 46FEB6A4087; Fri, 23 Oct 2015 03:01:50 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org, jim.bride@linux.intel.com, sivakumar.thulasimani@intel.com Date: Fri, 23 Oct 2015 13:02:00 +0300 Message-Id: <1445594525-7174-18-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1445594525-7174-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1445594525-7174-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH 17/22] drm/i915: Use struct intel_dp_signal_levels for eDP on SNB and IVB X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use the new struct intel_dp_signal_levels to store voltage swing and pre emphasis levels for eDP on SNB and IVB. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_dp_signal_levels.c | 132 ++++++++++++++++++-------- 1 file changed, 91 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp_signal_levels.c b/drivers/gpu/drm/i915/intel_dp_signal_levels.c index 365bdc4..aedd35b 100644 --- a/drivers/gpu/drm/i915/intel_dp_signal_levels.c +++ b/drivers/gpu/drm/i915/intel_dp_signal_levels.c @@ -443,7 +443,6 @@ static const struct signal_levels gen4_signal_levels = { .set = gen4_set_signal_levels, }; -/* Not for eDP */ static const struct signal_levels snb_signal_levels = { .max_voltage = DP_TRAIN_VOLTAGE_SWING_LEVEL_3, .max_pre_emph = { @@ -456,73 +455,123 @@ static const struct signal_levels snb_signal_levels = { .set = gen4_set_signal_levels, }; -/* Gen6's DP voltage swing and pre-emphasis control */ -static uint32_t -gen6_edp_signal_levels(uint8_t train_set) +/* SNB's DP voltage swing and pre-emphasis control */ +static void +snb_edp_set_signal_levels(struct intel_dp *intel_dp, uint8_t train_set) { - int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | - DP_TRAIN_PRE_EMPHASIS_MASK); - switch (signal_levels) { + uint32_t signal_levels; + + train_set &= + (DP_TRAIN_VOLTAGE_SWING_MASK | DP_TRAIN_PRE_EMPHASIS_MASK); + + switch (train_set) { case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: - return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; + signal_levels = EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; + break; case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: - return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; + signal_levels = EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; + break; case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: - return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; + signal_levels = EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; + break; case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: - return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; + signal_levels = EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; + break; case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: - return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; + signal_levels = EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; + break; default: DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" - "0x%x\n", signal_levels); - return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; + "0x%x\n", train_set); + signal_levels = EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; } + + DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); + + intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; + intel_dp->DP |= signal_levels; } -/* Gen7's DP voltage swing and pre-emphasis control */ -static uint32_t -gen7_edp_signal_levels(uint8_t train_set) +static const struct signal_levels snb_edp_signal_levels = { + .max_voltage = DP_TRAIN_VOLTAGE_SWING_LEVEL_2, + .max_pre_emph = { + DP_TRAIN_PRE_EMPH_LEVEL_2, + DP_TRAIN_PRE_EMPH_LEVEL_2, + DP_TRAIN_PRE_EMPH_LEVEL_1, + DP_TRAIN_PRE_EMPH_LEVEL_0, + }, + + .set = snb_edp_set_signal_levels, +}; + +/* IVB's DP voltage swing and pre-emphasis control */ +static void +ivb_edp_set_signal_levels(struct intel_dp *intel_dp, uint8_t train_set) { - int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | - DP_TRAIN_PRE_EMPHASIS_MASK); - switch (signal_levels) { + uint32_t signal_levels; + + train_set &= + (DP_TRAIN_VOLTAGE_SWING_MASK | DP_TRAIN_PRE_EMPHASIS_MASK); + + switch (train_set) { case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: - return EDP_LINK_TRAIN_400MV_0DB_IVB; + signal_levels = EDP_LINK_TRAIN_400MV_0DB_IVB; + break; case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: - return EDP_LINK_TRAIN_400MV_3_5DB_IVB; + signal_levels = EDP_LINK_TRAIN_400MV_3_5DB_IVB; + break; case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: - return EDP_LINK_TRAIN_400MV_6DB_IVB; + signal_levels = EDP_LINK_TRAIN_400MV_6DB_IVB; + break; case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: - return EDP_LINK_TRAIN_600MV_0DB_IVB; + signal_levels = EDP_LINK_TRAIN_600MV_0DB_IVB; + break; case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: - return EDP_LINK_TRAIN_600MV_3_5DB_IVB; + signal_levels = EDP_LINK_TRAIN_600MV_3_5DB_IVB; + break; case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: - return EDP_LINK_TRAIN_800MV_0DB_IVB; + signal_levels = EDP_LINK_TRAIN_800MV_0DB_IVB; + break; case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: - return EDP_LINK_TRAIN_800MV_3_5DB_IVB; + signal_levels = EDP_LINK_TRAIN_800MV_3_5DB_IVB; + break; default: DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" - "0x%x\n", signal_levels); - return EDP_LINK_TRAIN_500MV_0DB_IVB; + "0x%x\n", train_set); + signal_levels = EDP_LINK_TRAIN_500MV_0DB_IVB; } + + DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); + + intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; + intel_dp->DP |= signal_levels; } +static const struct signal_levels ivb_edp_signal_levels = { + .max_voltage = DP_TRAIN_VOLTAGE_SWING_LEVEL_2, + .max_pre_emph = { + DP_TRAIN_PRE_EMPH_LEVEL_2, + DP_TRAIN_PRE_EMPH_LEVEL_1, + DP_TRAIN_PRE_EMPH_LEVEL_1, + DP_TRAIN_PRE_EMPH_LEVEL_0, + }, + + .set = ivb_edp_set_signal_levels, +}; + static void _update_signal_levels(struct intel_dp *intel_dp) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - enum port port = intel_dig_port->port; struct drm_device *dev = intel_dig_port->base.base.dev; uint32_t signal_levels, mask = 0; - uint8_t train_set = intel_dp->train_set[0]; if (HAS_DDI(dev)) { signal_levels = ddi_signal_levels(intel_dp); @@ -535,12 +584,6 @@ _update_signal_levels(struct intel_dp *intel_dp) signal_levels = chv_signal_levels(intel_dp); } else if (IS_VALLEYVIEW(dev)) { signal_levels = vlv_signal_levels(intel_dp); - } else if (IS_GEN7(dev) && port == PORT_A) { - signal_levels = gen7_edp_signal_levels(train_set); - mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; - } else if (IS_GEN6(dev) && port == PORT_A) { - signal_levels = gen6_edp_signal_levels(train_set); - mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; } else { WARN(1, "Should be calling intel_dp->signal_levels->set instead."); return; @@ -599,9 +642,16 @@ intel_dp_init_signal_levels(struct intel_dp *intel_dp) struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); enum port port = intel_dig_port->port; - if (port != PORT_A && (IS_IVYBRIDGE(dev) || IS_GEN6(dev))) - intel_dp->signal_levels = &snb_signal_levels; - - if (INTEL_INFO(dev)->gen <= 5) + if (IS_IVYBRIDGE(dev)) { + if (port == PORT_A) + intel_dp->signal_levels = &ivb_edp_signal_levels; + else + intel_dp->signal_levels = &snb_signal_levels; + } else if (IS_GEN6(dev)) { + if (port == PORT_A) + intel_dp->signal_levels = &snb_edp_signal_levels; + else + intel_dp->signal_levels = &snb_signal_levels; + } else if (INTEL_INFO(dev)->gen <= 5) intel_dp->signal_levels = &gen4_signal_levels; }