From patchwork Fri Oct 23 10:02:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 7471511 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E071C9F1C3 for ; Fri, 23 Oct 2015 10:03:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0784E206E3 for ; Fri, 23 Oct 2015 10:03:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 1DEA320667 for ; Fri, 23 Oct 2015 10:03:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4BD95722C3; Fri, 23 Oct 2015 03:03:00 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id EBD43722BC for ; Fri, 23 Oct 2015 03:02:57 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP; 23 Oct 2015 03:02:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,186,1444719600"; d="scan'208";a="833325452" Received: from linux.intel.com ([10.23.219.25]) by orsmga002.jf.intel.com with ESMTP; 23 Oct 2015 03:02:57 -0700 Received: from localhost (aconselv-mobl3.ger.corp.intel.com [10.252.19.216]) by linux.intel.com (Postfix) with ESMTP id 05B116A4083; Fri, 23 Oct 2015 03:01:56 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org, jim.bride@linux.intel.com, sivakumar.thulasimani@intel.com Date: Fri, 23 Oct 2015 13:02:02 +0300 Message-Id: <1445594525-7174-20-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1445594525-7174-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1445594525-7174-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH 19/22] drm/i915: Use struct intel_dp_signal_levels for CHV X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use the new struct intel_dp_signal_levels to store voltage swing and pre emphasis levels for CHV. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_dp_signal_levels.c | 38 ++++++++++++++++++--------- 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp_signal_levels.c b/drivers/gpu/drm/i915/intel_dp_signal_levels.c index 1d07f46..3f396b1 100644 --- a/drivers/gpu/drm/i915/intel_dp_signal_levels.c +++ b/drivers/gpu/drm/i915/intel_dp_signal_levels.c @@ -235,14 +235,13 @@ static bool chv_need_uniq_trans_scale(uint8_t train_set) (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3; } -static uint32_t chv_signal_levels(struct intel_dp *intel_dp) +static void chv_set_signal_levels(struct intel_dp *intel_dp, uint8_t train_set) { struct drm_device *dev = intel_dp_to_dev(intel_dp); struct drm_i915_private *dev_priv = dev->dev_private; struct intel_digital_port *dport = dp_to_dig_port(intel_dp); struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); u32 deemph_reg_value, margin_reg_value, val; - uint8_t train_set = intel_dp->train_set[0]; enum dpio_channel ch = vlv_dport_to_channel(dport); enum pipe pipe = intel_crtc->pipe; int i; @@ -268,7 +267,8 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp) /* FIXME extra to set for 1200 */ break; default: - return 0; + MISSING_CASE(train_set & DP_TRAIN_VOLTAGE_SWING_MASK); + return; } break; case DP_TRAIN_PRE_EMPH_LEVEL_1: @@ -286,7 +286,8 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp) margin_reg_value = 154; break; default: - return 0; + MISSING_CASE(train_set & DP_TRAIN_VOLTAGE_SWING_MASK); + return; } break; case DP_TRAIN_PRE_EMPH_LEVEL_2: @@ -300,7 +301,8 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp) margin_reg_value = 154; break; default: - return 0; + MISSING_CASE(train_set & DP_TRAIN_VOLTAGE_SWING_MASK); + return; } break; case DP_TRAIN_PRE_EMPH_LEVEL_3: @@ -310,11 +312,13 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp) margin_reg_value = 154; break; default: - return 0; + MISSING_CASE(train_set & DP_TRAIN_VOLTAGE_SWING_MASK); + return; } break; default: - return 0; + MISSING_CASE(train_set & DP_TRAIN_PRE_EMPHASIS_MASK); + return; } mutex_lock(&dev_priv->sb_lock); @@ -399,10 +403,20 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp) } mutex_unlock(&dev_priv->sb_lock); - - return 0; } +static const struct signal_levels chv_signal_levels = { + .max_voltage = DP_TRAIN_VOLTAGE_SWING_LEVEL_3, + .max_pre_emph = { + DP_TRAIN_PRE_EMPH_LEVEL_3, + DP_TRAIN_PRE_EMPH_LEVEL_2, + DP_TRAIN_PRE_EMPH_LEVEL_1, + DP_TRAIN_PRE_EMPH_LEVEL_0, + }, + + .set = chv_set_signal_levels, +}; + static void gen4_set_signal_levels(struct intel_dp *intel_dp, uint8_t train_set) { @@ -594,8 +608,6 @@ _update_signal_levels(struct intel_dp *intel_dp) signal_levels = 0; else mask = DDI_BUF_EMP_MASK; - } else if (IS_CHERRYVIEW(dev)) { - signal_levels = chv_signal_levels(intel_dp); } else { WARN(1, "Should be calling intel_dp->signal_levels->set instead."); return; @@ -654,7 +666,9 @@ intel_dp_init_signal_levels(struct intel_dp *intel_dp) struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); enum port port = intel_dig_port->port; - if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { + if (IS_CHERRYVIEW(dev)) { + intel_dp->signal_levels = &chv_signal_levels; + } else if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { intel_dp->signal_levels = &vlv_signal_levels; } else if (IS_IVYBRIDGE(dev)) { if (port == PORT_A)