From patchwork Fri Oct 23 10:02:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 7471551 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B0450BEEA4 for ; Fri, 23 Oct 2015 10:03:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CE3BC20667 for ; Fri, 23 Oct 2015 10:03:27 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D47BD2083E for ; Fri, 23 Oct 2015 10:03:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 350B76E421; Fri, 23 Oct 2015 03:03:26 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E3DD721C9 for ; Fri, 23 Oct 2015 03:03:25 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 23 Oct 2015 03:02:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,186,1444719600"; d="scan'208";a="801008123" Received: from linux.intel.com ([10.23.219.25]) by orsmga001.jf.intel.com with ESMTP; 23 Oct 2015 03:02:59 -0700 Received: from localhost (aconselv-mobl3.ger.corp.intel.com [10.252.19.216]) by linux.intel.com (Postfix) with ESMTP id 2C5A86A4083; Fri, 23 Oct 2015 03:01:58 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org, jim.bride@linux.intel.com, sivakumar.thulasimani@intel.com Date: Fri, 23 Oct 2015 13:02:03 +0300 Message-Id: <1445594525-7174-21-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1445594525-7174-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1445594525-7174-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH 20/22] drm/i915: Use struct intel_dp_signal_levels for DDI platforms X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use the new struct intel_dp_signal_levels to store voltage swing and pre emphasis levels for DDI platforms. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_dp_signal_levels.c | 63 ++++++++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp_signal_levels.c b/drivers/gpu/drm/i915/intel_dp_signal_levels.c index 3f396b1..d1eccd7 100644 --- a/drivers/gpu/drm/i915/intel_dp_signal_levels.c +++ b/drivers/gpu/drm/i915/intel_dp_signal_levels.c @@ -115,6 +115,59 @@ _dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) } } +static void +hsw_set_signal_levels(struct intel_dp *intel_dp, uint8_t train_set) +{ + uint32_t signal_levels = ddi_signal_levels(intel_dp); + + DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); + + intel_dp->DP &= ~DDI_BUF_EMP_MASK; + intel_dp->DP |= signal_levels; +} + +static const struct signal_levels hsw_signal_levels = { + .max_voltage = DP_TRAIN_VOLTAGE_SWING_LEVEL_2, + .max_pre_emph = { + DP_TRAIN_PRE_EMPH_LEVEL_3, + DP_TRAIN_PRE_EMPH_LEVEL_2, + DP_TRAIN_PRE_EMPH_LEVEL_1, + DP_TRAIN_PRE_EMPH_LEVEL_0, + }, + + .set = hsw_set_signal_levels, +}; + +static const struct signal_levels skl_edp_low_vswing_signal_levels = { + .max_voltage = DP_TRAIN_VOLTAGE_SWING_LEVEL_3, + .max_pre_emph = { + DP_TRAIN_PRE_EMPH_LEVEL_3, + DP_TRAIN_PRE_EMPH_LEVEL_2, + DP_TRAIN_PRE_EMPH_LEVEL_1, + DP_TRAIN_PRE_EMPH_LEVEL_0, + }, + + .set = hsw_set_signal_levels, +}; + +static void +bxt_set_signal_levels(struct intel_dp *intel_dp, uint8_t train_set) +{ + ddi_signal_levels(intel_dp); +} + +static const struct signal_levels bxt_signal_levels = { + .max_voltage = DP_TRAIN_VOLTAGE_SWING_LEVEL_3, + .max_pre_emph = { + DP_TRAIN_PRE_EMPH_LEVEL_3, + DP_TRAIN_PRE_EMPH_LEVEL_2, + DP_TRAIN_PRE_EMPH_LEVEL_1, + DP_TRAIN_PRE_EMPH_LEVEL_0, + }, + + .set = bxt_set_signal_levels, +}; + static void vlv_set_signal_levels(struct intel_dp *intel_dp, uint8_t train_set) { struct drm_device *dev = intel_dp_to_dev(intel_dp); @@ -663,10 +716,18 @@ void intel_dp_init_signal_levels(struct intel_dp *intel_dp) { struct drm_device *dev = intel_dp_to_dev(intel_dp); + struct drm_i915_private *dev_priv = to_i915(dev); struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); enum port port = intel_dig_port->port; - if (IS_CHERRYVIEW(dev)) { + if (IS_BROXTON(dev)) { + intel_dp->signal_levels = &bxt_signal_levels; + } else if (IS_SKYLAKE(dev) && + port == PORT_A && dev_priv->edp_low_vswing) { + intel_dp->signal_levels = &skl_edp_low_vswing_signal_levels; + } else if (HAS_DDI(dev)) { + intel_dp->signal_levels = &hsw_signal_levels; + } else if (IS_CHERRYVIEW(dev)) { intel_dp->signal_levels = &chv_signal_levels; } else if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { intel_dp->signal_levels = &vlv_signal_levels;