diff mbox

[RFC] drm/i915/bxt: Added identifier for MIPI transcoder

Message ID 1445933147-26688-1-git-send-email-animesh.manna@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Manna, Animesh Oct. 27, 2015, 8:05 a.m. UTC 
Changes done:
- Added identifier for Mipi transcoder A and C.
- Added power domain identifier for newly added mipi trancoder.
- Initialized transcoder for mipi during compute config.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c     | 4 ++++
 drivers/gpu/drm/i915/i915_drv.h         | 4 ++++
 drivers/gpu/drm/i915/intel_dsi.c        | 8 ++++++++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
 4 files changed, 18 insertions(+)

Comments

kernel test robot Oct. 27, 2015, 8:26 a.m. UTC | #1 
Hi Animesh,

[auto build test ERROR on drm-intel/for-linux-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base]

url:    https://github.com/0day-ci/linux/commits/Animesh-Manna/drm-i915-bxt-Added-identifier-for-MIPI-transcoder/20151027-160751
config: i386-defconfig (attached as .config)
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All error/warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_runtime_pm.c: In function 'lookup_power_well':
   include/linux/bitops.h:6:24: warning: left shift count >= width of type [-Wshift-count-overflow]
    #define BIT(nr)   (1UL << (nr))
                           ^
   drivers/gpu/drm/i915/intel_runtime_pm.c:60:32: note: in definition of macro 'for_each_power_well'
      if ((power_well)->domains & (domain_mask))
                                   ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:971:28: note: in expansion of macro 'BIT'
    #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
                               ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:980:37: note: in expansion of macro 'POWER_DOMAIN_MASK'
     for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
                                        ^
   In file included from include/linux/kernel.h:10:0,
                    from include/linux/list.h:8,
                    from include/linux/kobject.h:20,
                    from include/linux/device.h:17,
                    from include/linux/pm_runtime.h:12,
                    from drivers/gpu/drm/i915/intel_runtime_pm.c:29:
   drivers/gpu/drm/i915/intel_runtime_pm.c: At top level:
   include/linux/bitops.h:6:24: warning: left shift count >= width of type [-Wshift-count-overflow]
    #define BIT(nr)   (1UL << (nr))
                           ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:971:28: note: in expansion of macro 'BIT'
    #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
                               ^
   drivers/gpu/drm/i915/intel_runtime_pm.c:1574:14: note: in expansion of macro 'POWER_DOMAIN_MASK'
      .domains = POWER_DOMAIN_MASK,
                 ^
   include/linux/bitops.h:6:24: warning: left shift count >= width of type [-Wshift-count-overflow]
    #define BIT(nr)   (1UL << (nr))
                           ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:971:28: note: in expansion of macro 'BIT'
    #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
                               ^
   drivers/gpu/drm/i915/intel_runtime_pm.c:1489:3: note: in expansion of macro 'POWER_DOMAIN_MASK'
     (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
      ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:1602:14: note: in expansion of macro 'HSW_DISPLAY_POWER_DOMAINS'
      .domains = HSW_DISPLAY_POWER_DOMAINS,
                 ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:1488:35: error: initializer element is not constant
    #define HSW_DISPLAY_POWER_DOMAINS (    \
                                      ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:1602:14: note: in expansion of macro 'HSW_DISPLAY_POWER_DOMAINS'
      .domains = HSW_DISPLAY_POWER_DOMAINS,
                 ^
   drivers/gpu/drm/i915/intel_runtime_pm.c:1488:35: note: (near initialization for 'hsw_power_wells[1].domains')
    #define HSW_DISPLAY_POWER_DOMAINS (    \
                                      ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:1602:14: note: in expansion of macro 'HSW_DISPLAY_POWER_DOMAINS'
      .domains = HSW_DISPLAY_POWER_DOMAINS,
                 ^
   In file included from include/linux/kernel.h:10:0,
                    from include/linux/list.h:8,
                    from include/linux/kobject.h:20,
                    from include/linux/device.h:17,
                    from include/linux/pm_runtime.h:12,
                    from drivers/gpu/drm/i915/intel_runtime_pm.c:29:
   include/linux/bitops.h:6:24: warning: left shift count >= width of type [-Wshift-count-overflow]
    #define BIT(nr)   (1UL << (nr))
                           ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:971:28: note: in expansion of macro 'BIT'
    #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
                               ^
   drivers/gpu/drm/i915/intel_runtime_pm.c:1496:3: note: in expansion of macro 'POWER_DOMAIN_MASK'
     (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
      ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:1616:14: note: in expansion of macro 'BDW_DISPLAY_POWER_DOMAINS'
      .domains = BDW_DISPLAY_POWER_DOMAINS,
                 ^
   drivers/gpu/drm/i915/intel_runtime_pm.c:1495:35: error: initializer element is not constant
    #define BDW_DISPLAY_POWER_DOMAINS (    \
                                      ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:1616:14: note: in expansion of macro 'BDW_DISPLAY_POWER_DOMAINS'
      .domains = BDW_DISPLAY_POWER_DOMAINS,
                 ^
   drivers/gpu/drm/i915/intel_runtime_pm.c:1495:35: note: (near initialization for 'bdw_power_wells[1].domains')
    #define BDW_DISPLAY_POWER_DOMAINS (    \
                                      ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:1616:14: note: in expansion of macro 'BDW_DISPLAY_POWER_DOMAINS'
      .domains = BDW_DISPLAY_POWER_DOMAINS,
                 ^
   In file included from include/linux/kernel.h:10:0,
                    from include/linux/list.h:8,
                    from include/linux/kobject.h:20,
                    from include/linux/device.h:17,
                    from include/linux/pm_runtime.h:12,
                    from drivers/gpu/drm/i915/intel_runtime_pm.c:29:
   include/linux/bitops.h:6:24: warning: left shift count >= width of type [-Wshift-count-overflow]
    #define BIT(nr)   (1UL << (nr))
                           ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:971:28: note: in expansion of macro 'BIT'
    #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
                               ^
   drivers/gpu/drm/i915/intel_runtime_pm.c:1500:35: note: in expansion of macro 'POWER_DOMAIN_MASK'
    #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
                                      ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:1651:14: note: in expansion of macro 'VLV_DISPLAY_POWER_DOMAINS'
      .domains = VLV_DISPLAY_POWER_DOMAINS,
                 ^
   include/linux/bitops.h:6:24: warning: left shift count >= width of type [-Wshift-count-overflow]
    #define BIT(nr)   (1UL << (nr))
                           ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:971:28: note: in expansion of macro 'BIT'
    #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
                               ^
   drivers/gpu/drm/i915/intel_runtime_pm.c:1500:35: note: in expansion of macro 'POWER_DOMAIN_MASK'
    #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
                                      ^
   drivers/gpu/drm/i915/intel_runtime_pm.c:1713:14: note: in expansion of macro 'VLV_DISPLAY_POWER_DOMAINS'
      .domains = VLV_DISPLAY_POWER_DOMAINS,
                 ^
   include/linux/bitops.h:6:24: warning: left shift count >= width of type [-Wshift-count-overflow]
    #define BIT(nr)   (1UL << (nr))
                           ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:971:28: note: in expansion of macro 'BIT'
    #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
                               ^
   drivers/gpu/drm/i915/intel_runtime_pm.c:339:3: note: in expansion of macro 'POWER_DOMAIN_MASK'
     (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
      ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:1747:14: note: in expansion of macro 'SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS'
      .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
                 ^
   drivers/gpu/drm/i915/intel_runtime_pm.c:338:45: error: initializer element is not constant
    #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (  \
                                                ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:1747:14: note: in expansion of macro 'SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS'
      .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
                 ^
   drivers/gpu/drm/i915/intel_runtime_pm.c:338:45: note: (near initialization for 'skl_power_wells[0].domains')
    #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (  \
                                                ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:1747:14: note: in expansion of macro 'SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS'
      .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
                 ^
   In file included from include/linux/kernel.h:10:0,
                    from include/linux/list.h:8,
                    from include/linux/kobject.h:20,
                    from include/linux/device.h:17,
                    from include/linux/pm_runtime.h:12,
                    from drivers/gpu/drm/i915/intel_runtime_pm.c:29:
   include/linux/bitops.h:6:24: warning: left shift count >= width of type [-Wshift-count-overflow]
    #define BIT(nr)   (1UL << (nr))
                           ^
>> drivers/gpu/drm/i915/intel_runtime_pm.c:971:28: note: in expansion of macro 'BIT'
    #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
                               ^
   drivers/gpu/drm/i915/intel_runtime_pm.c:378:3: note: in expansion of macro 'POWER_DOMAIN_MASK'
     (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
      ^

vim +1488 drivers/gpu/drm/i915/intel_runtime_pm.c

9c065a7d Daniel Vetter      2014-09-30  1482  	BIT(POWER_DOMAIN_PLLS) |			\
1407121a Satheeshakrishna M 2015-01-16  1483  	BIT(POWER_DOMAIN_AUX_A) |			\
1407121a Satheeshakrishna M 2015-01-16  1484  	BIT(POWER_DOMAIN_AUX_B) |			\
1407121a Satheeshakrishna M 2015-01-16  1485  	BIT(POWER_DOMAIN_AUX_C) |			\
1407121a Satheeshakrishna M 2015-01-16  1486  	BIT(POWER_DOMAIN_AUX_D) |			\
9c065a7d Daniel Vetter      2014-09-30  1487  	BIT(POWER_DOMAIN_INIT))
9c065a7d Daniel Vetter      2014-09-30 @1488  #define HSW_DISPLAY_POWER_DOMAINS (				\
9c065a7d Daniel Vetter      2014-09-30  1489  	(POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |	\
9c065a7d Daniel Vetter      2014-09-30  1490  	BIT(POWER_DOMAIN_INIT))
9c065a7d Daniel Vetter      2014-09-30  1491  
9c065a7d Daniel Vetter      2014-09-30  1492  #define BDW_ALWAYS_ON_POWER_DOMAINS (			\
9c065a7d Daniel Vetter      2014-09-30  1493  	HSW_ALWAYS_ON_POWER_DOMAINS |			\
9c065a7d Daniel Vetter      2014-09-30  1494  	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
9c065a7d Daniel Vetter      2014-09-30  1495  #define BDW_DISPLAY_POWER_DOMAINS (				\
9c065a7d Daniel Vetter      2014-09-30  1496  	(POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |	\
9c065a7d Daniel Vetter      2014-09-30  1497  	BIT(POWER_DOMAIN_INIT))
9c065a7d Daniel Vetter      2014-09-30  1498  
9c065a7d Daniel Vetter      2014-09-30  1499  #define VLV_ALWAYS_ON_POWER_DOMAINS	BIT(POWER_DOMAIN_INIT)
9c065a7d Daniel Vetter      2014-09-30  1500  #define VLV_DISPLAY_POWER_DOMAINS	POWER_DOMAIN_MASK
9c065a7d Daniel Vetter      2014-09-30  1501  
9c065a7d Daniel Vetter      2014-09-30  1502  #define VLV_DPIO_CMN_BC_POWER_DOMAINS (		\
9c065a7d Daniel Vetter      2014-09-30  1503  	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |	\
9c065a7d Daniel Vetter      2014-09-30  1504  	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |	\
9c065a7d Daniel Vetter      2014-09-30  1505  	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |	\
9c065a7d Daniel Vetter      2014-09-30  1506  	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |	\
9c065a7d Daniel Vetter      2014-09-30  1507  	BIT(POWER_DOMAIN_PORT_CRT) |		\
1407121a Satheeshakrishna M 2015-01-16  1508  	BIT(POWER_DOMAIN_AUX_B) |		\
1407121a Satheeshakrishna M 2015-01-16  1509  	BIT(POWER_DOMAIN_AUX_C) |		\
9c065a7d Daniel Vetter      2014-09-30  1510  	BIT(POWER_DOMAIN_INIT))
9c065a7d Daniel Vetter      2014-09-30  1511  
9c065a7d Daniel Vetter      2014-09-30  1512  #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (	\
9c065a7d Daniel Vetter      2014-09-30  1513  	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |	\
9c065a7d Daniel Vetter      2014-09-30  1514  	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |	\
1407121a Satheeshakrishna M 2015-01-16  1515  	BIT(POWER_DOMAIN_AUX_B) |		\
9c065a7d Daniel Vetter      2014-09-30  1516  	BIT(POWER_DOMAIN_INIT))
9c065a7d Daniel Vetter      2014-09-30  1517  
9c065a7d Daniel Vetter      2014-09-30  1518  #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (	\
9c065a7d Daniel Vetter      2014-09-30  1519  	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |	\
1407121a Satheeshakrishna M 2015-01-16  1520  	BIT(POWER_DOMAIN_AUX_B) |		\
9c065a7d Daniel Vetter      2014-09-30  1521  	BIT(POWER_DOMAIN_INIT))
9c065a7d Daniel Vetter      2014-09-30  1522  
9c065a7d Daniel Vetter      2014-09-30  1523  #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (	\
9c065a7d Daniel Vetter      2014-09-30  1524  	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |	\
9c065a7d Daniel Vetter      2014-09-30  1525  	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |	\
1407121a Satheeshakrishna M 2015-01-16  1526  	BIT(POWER_DOMAIN_AUX_C) |		\
9c065a7d Daniel Vetter      2014-09-30  1527  	BIT(POWER_DOMAIN_INIT))
9c065a7d Daniel Vetter      2014-09-30  1528  
9c065a7d Daniel Vetter      2014-09-30  1529  #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (	\
9c065a7d Daniel Vetter      2014-09-30  1530  	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |	\
1407121a Satheeshakrishna M 2015-01-16  1531  	BIT(POWER_DOMAIN_AUX_C) |		\
9c065a7d Daniel Vetter      2014-09-30  1532  	BIT(POWER_DOMAIN_INIT))
9c065a7d Daniel Vetter      2014-09-30  1533  
9c065a7d Daniel Vetter      2014-09-30  1534  #define CHV_DPIO_CMN_BC_POWER_DOMAINS (		\
9c065a7d Daniel Vetter      2014-09-30  1535  	BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |	\
9c065a7d Daniel Vetter      2014-09-30  1536  	BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |	\
9c065a7d Daniel Vetter      2014-09-30  1537  	BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |	\
9c065a7d Daniel Vetter      2014-09-30  1538  	BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |	\
1407121a Satheeshakrishna M 2015-01-16  1539  	BIT(POWER_DOMAIN_AUX_B) |		\
1407121a Satheeshakrishna M 2015-01-16  1540  	BIT(POWER_DOMAIN_AUX_C) |		\
9c065a7d Daniel Vetter      2014-09-30  1541  	BIT(POWER_DOMAIN_INIT))
9c065a7d Daniel Vetter      2014-09-30  1542  
9c065a7d Daniel Vetter      2014-09-30  1543  #define CHV_DPIO_CMN_D_POWER_DOMAINS (		\
9c065a7d Daniel Vetter      2014-09-30  1544  	BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |	\
9c065a7d Daniel Vetter      2014-09-30  1545  	BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |	\
1407121a Satheeshakrishna M 2015-01-16  1546  	BIT(POWER_DOMAIN_AUX_D) |		\
9c065a7d Daniel Vetter      2014-09-30  1547  	BIT(POWER_DOMAIN_INIT))
9c065a7d Daniel Vetter      2014-09-30  1548  
9c065a7d Daniel Vetter      2014-09-30  1549  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
9c065a7d Daniel Vetter      2014-09-30  1550  	.sync_hw = i9xx_always_on_power_well_noop,
9c065a7d Daniel Vetter      2014-09-30  1551  	.enable = i9xx_always_on_power_well_noop,
9c065a7d Daniel Vetter      2014-09-30  1552  	.disable = i9xx_always_on_power_well_noop,
9c065a7d Daniel Vetter      2014-09-30  1553  	.is_enabled = i9xx_always_on_power_well_enabled,
9c065a7d Daniel Vetter      2014-09-30  1554  };
9c065a7d Daniel Vetter      2014-09-30  1555  
9c065a7d Daniel Vetter      2014-09-30  1556  static const struct i915_power_well_ops chv_pipe_power_well_ops = {
9c065a7d Daniel Vetter      2014-09-30  1557  	.sync_hw = chv_pipe_power_well_sync_hw,
9c065a7d Daniel Vetter      2014-09-30  1558  	.enable = chv_pipe_power_well_enable,
9c065a7d Daniel Vetter      2014-09-30  1559  	.disable = chv_pipe_power_well_disable,
9c065a7d Daniel Vetter      2014-09-30  1560  	.is_enabled = chv_pipe_power_well_enabled,
9c065a7d Daniel Vetter      2014-09-30  1561  };
9c065a7d Daniel Vetter      2014-09-30  1562  
9c065a7d Daniel Vetter      2014-09-30  1563  static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
9c065a7d Daniel Vetter      2014-09-30  1564  	.sync_hw = vlv_power_well_sync_hw,
9c065a7d Daniel Vetter      2014-09-30  1565  	.enable = chv_dpio_cmn_power_well_enable,
9c065a7d Daniel Vetter      2014-09-30  1566  	.disable = chv_dpio_cmn_power_well_disable,
9c065a7d Daniel Vetter      2014-09-30  1567  	.is_enabled = vlv_power_well_enabled,
9c065a7d Daniel Vetter      2014-09-30  1568  };
9c065a7d Daniel Vetter      2014-09-30  1569  
9c065a7d Daniel Vetter      2014-09-30  1570  static struct i915_power_well i9xx_always_on_power_well[] = {
9c065a7d Daniel Vetter      2014-09-30  1571  	{
9c065a7d Daniel Vetter      2014-09-30  1572  		.name = "always-on",
9c065a7d Daniel Vetter      2014-09-30  1573  		.always_on = 1,
9c065a7d Daniel Vetter      2014-09-30  1574  		.domains = POWER_DOMAIN_MASK,
9c065a7d Daniel Vetter      2014-09-30  1575  		.ops = &i9xx_always_on_power_well_ops,
9c065a7d Daniel Vetter      2014-09-30  1576  	},
9c065a7d Daniel Vetter      2014-09-30  1577  };
9c065a7d Daniel Vetter      2014-09-30  1578  
9c065a7d Daniel Vetter      2014-09-30  1579  static const struct i915_power_well_ops hsw_power_well_ops = {
9c065a7d Daniel Vetter      2014-09-30  1580  	.sync_hw = hsw_power_well_sync_hw,
9c065a7d Daniel Vetter      2014-09-30  1581  	.enable = hsw_power_well_enable,
9c065a7d Daniel Vetter      2014-09-30  1582  	.disable = hsw_power_well_disable,
9c065a7d Daniel Vetter      2014-09-30  1583  	.is_enabled = hsw_power_well_enabled,
9c065a7d Daniel Vetter      2014-09-30  1584  };
9c065a7d Daniel Vetter      2014-09-30  1585  
94dd5138 Satheeshakrishna M 2015-02-04  1586  static const struct i915_power_well_ops skl_power_well_ops = {
94dd5138 Satheeshakrishna M 2015-02-04  1587  	.sync_hw = skl_power_well_sync_hw,
94dd5138 Satheeshakrishna M 2015-02-04  1588  	.enable = skl_power_well_enable,
94dd5138 Satheeshakrishna M 2015-02-04  1589  	.disable = skl_power_well_disable,
94dd5138 Satheeshakrishna M 2015-02-04  1590  	.is_enabled = skl_power_well_enabled,
94dd5138 Satheeshakrishna M 2015-02-04  1591  };
94dd5138 Satheeshakrishna M 2015-02-04  1592  
9c065a7d Daniel Vetter      2014-09-30  1593  static struct i915_power_well hsw_power_wells[] = {
9c065a7d Daniel Vetter      2014-09-30  1594  	{
9c065a7d Daniel Vetter      2014-09-30  1595  		.name = "always-on",
9c065a7d Daniel Vetter      2014-09-30  1596  		.always_on = 1,
9c065a7d Daniel Vetter      2014-09-30  1597  		.domains = HSW_ALWAYS_ON_POWER_DOMAINS,
9c065a7d Daniel Vetter      2014-09-30  1598  		.ops = &i9xx_always_on_power_well_ops,
9c065a7d Daniel Vetter      2014-09-30  1599  	},
9c065a7d Daniel Vetter      2014-09-30  1600  	{
9c065a7d Daniel Vetter      2014-09-30  1601  		.name = "display",
9c065a7d Daniel Vetter      2014-09-30 @1602  		.domains = HSW_DISPLAY_POWER_DOMAINS,
9c065a7d Daniel Vetter      2014-09-30  1603  		.ops = &hsw_power_well_ops,
9c065a7d Daniel Vetter      2014-09-30  1604  	},
9c065a7d Daniel Vetter      2014-09-30  1605  };
9c065a7d Daniel Vetter      2014-09-30  1606  
9c065a7d Daniel Vetter      2014-09-30  1607  static struct i915_power_well bdw_power_wells[] = {
9c065a7d Daniel Vetter      2014-09-30  1608  	{
9c065a7d Daniel Vetter      2014-09-30  1609  		.name = "always-on",
9c065a7d Daniel Vetter      2014-09-30  1610  		.always_on = 1,
9c065a7d Daniel Vetter      2014-09-30  1611  		.domains = BDW_ALWAYS_ON_POWER_DOMAINS,
9c065a7d Daniel Vetter      2014-09-30  1612  		.ops = &i9xx_always_on_power_well_ops,
9c065a7d Daniel Vetter      2014-09-30  1613  	},
9c065a7d Daniel Vetter      2014-09-30  1614  	{
9c065a7d Daniel Vetter      2014-09-30  1615  		.name = "display",
9c065a7d Daniel Vetter      2014-09-30 @1616  		.domains = BDW_DISPLAY_POWER_DOMAINS,
9c065a7d Daniel Vetter      2014-09-30  1617  		.ops = &hsw_power_well_ops,
9c065a7d Daniel Vetter      2014-09-30  1618  	},
9c065a7d Daniel Vetter      2014-09-30  1619  };
9c065a7d Daniel Vetter      2014-09-30  1620  
9c065a7d Daniel Vetter      2014-09-30  1621  static const struct i915_power_well_ops vlv_display_power_well_ops = {
9c065a7d Daniel Vetter      2014-09-30  1622  	.sync_hw = vlv_power_well_sync_hw,
9c065a7d Daniel Vetter      2014-09-30  1623  	.enable = vlv_display_power_well_enable,
9c065a7d Daniel Vetter      2014-09-30  1624  	.disable = vlv_display_power_well_disable,
9c065a7d Daniel Vetter      2014-09-30  1625  	.is_enabled = vlv_power_well_enabled,
9c065a7d Daniel Vetter      2014-09-30  1626  };
9c065a7d Daniel Vetter      2014-09-30  1627  
9c065a7d Daniel Vetter      2014-09-30  1628  static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
9c065a7d Daniel Vetter      2014-09-30  1629  	.sync_hw = vlv_power_well_sync_hw,
9c065a7d Daniel Vetter      2014-09-30  1630  	.enable = vlv_dpio_cmn_power_well_enable,
9c065a7d Daniel Vetter      2014-09-30  1631  	.disable = vlv_dpio_cmn_power_well_disable,
9c065a7d Daniel Vetter      2014-09-30  1632  	.is_enabled = vlv_power_well_enabled,
9c065a7d Daniel Vetter      2014-09-30  1633  };
9c065a7d Daniel Vetter      2014-09-30  1634  
9c065a7d Daniel Vetter      2014-09-30  1635  static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
9c065a7d Daniel Vetter      2014-09-30  1636  	.sync_hw = vlv_power_well_sync_hw,
9c065a7d Daniel Vetter      2014-09-30  1637  	.enable = vlv_power_well_enable,
9c065a7d Daniel Vetter      2014-09-30  1638  	.disable = vlv_power_well_disable,
9c065a7d Daniel Vetter      2014-09-30  1639  	.is_enabled = vlv_power_well_enabled,
9c065a7d Daniel Vetter      2014-09-30  1640  };
9c065a7d Daniel Vetter      2014-09-30  1641  
9c065a7d Daniel Vetter      2014-09-30  1642  static struct i915_power_well vlv_power_wells[] = {
9c065a7d Daniel Vetter      2014-09-30  1643  	{
9c065a7d Daniel Vetter      2014-09-30  1644  		.name = "always-on",
9c065a7d Daniel Vetter      2014-09-30  1645  		.always_on = 1,
9c065a7d Daniel Vetter      2014-09-30  1646  		.domains = VLV_ALWAYS_ON_POWER_DOMAINS,
9c065a7d Daniel Vetter      2014-09-30  1647  		.ops = &i9xx_always_on_power_well_ops,
9c065a7d Daniel Vetter      2014-09-30  1648  	},
9c065a7d Daniel Vetter      2014-09-30  1649  	{
9c065a7d Daniel Vetter      2014-09-30  1650  		.name = "display",
9c065a7d Daniel Vetter      2014-09-30 @1651  		.domains = VLV_DISPLAY_POWER_DOMAINS,
9c065a7d Daniel Vetter      2014-09-30  1652  		.data = PUNIT_POWER_WELL_DISP2D,
9c065a7d Daniel Vetter      2014-09-30  1653  		.ops = &vlv_display_power_well_ops,
9c065a7d Daniel Vetter      2014-09-30  1654  	},

:::::: The code at line 1488 was first introduced by commit
:::::: 9c065a7d5b679e7fabe3cace4faadb283f2b0c1f drm/i915: Extract intel_runtime_pm.c

:::::: TO: Daniel Vetter <daniel.vetter@ffwll.ch>
:::::: CC: Daniel Vetter <daniel.vetter@ffwll.ch>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index eca94d0..a8b45f2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2700,6 +2700,10 @@  static const char *power_domain_str(enum intel_display_power_domain domain)
 		return "TRANSCODER_B";
 	case POWER_DOMAIN_TRANSCODER_C:
 		return "TRANSCODER_C";
+	case POWER_DOMAIN_TRANSCODER_MIPI_A:
+		return "TRANSCODER_MIPI_A";
+	case POWER_DOMAIN_TRANSCODER_MIPI_C:
+		return "TRANSCODER_MIPI_C";
 	case POWER_DOMAIN_TRANSCODER_EDP:
 		return "TRANSCODER_EDP";
 	case POWER_DOMAIN_PORT_DDI_A_2_LANES:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index be37f0c..3d8ca48 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -126,6 +126,8 @@  enum transcoder {
 	TRANSCODER_B,
 	TRANSCODER_C,
 	TRANSCODER_EDP,
+	TRANSCODER_MIPI_A,
+	TRANSCODER_MIPI_C,
 	I915_MAX_TRANSCODERS
 };
 #define transcoder_name(t) ((t) + 'A')
@@ -180,6 +182,8 @@  enum intel_display_power_domain {
 	POWER_DOMAIN_TRANSCODER_B,
 	POWER_DOMAIN_TRANSCODER_C,
 	POWER_DOMAIN_TRANSCODER_EDP,
+	POWER_DOMAIN_TRANSCODER_MIPI_A,
+	POWER_DOMAIN_TRANSCODER_MIPI_C,
 	POWER_DOMAIN_PORT_DDI_A_2_LANES,
 	POWER_DOMAIN_PORT_DDI_A_4_LANES,
 	POWER_DOMAIN_PORT_DDI_B_2_LANES,
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 170ae6f..cb3160f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -270,6 +270,7 @@  static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 	struct intel_connector *intel_connector = intel_dsi->attached_connector;
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 	struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode;
+	struct drm_device *dev = intel_connector->base.dev;
 
 	DRM_DEBUG_KMS("\n");
 
@@ -279,6 +280,13 @@  static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 	/* DSI uses short packets for sync events, so clear mode flags for DSI */
 	adjusted_mode->flags = 0;
 
+	if (IS_BROXTON(dev)) {
+		if (intel_dsi->ports & (1 << PORT_A))
+			config->cpu_transcoder = TRANSCODER_MIPI_A;
+		else
+			config->cpu_transcoder = TRANSCODER_MIPI_C;
+	}
+
 	return true;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index e50cc88..06b58eb 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -367,6 +367,8 @@  static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |		\
 	BIT(POWER_DOMAIN_PIPE_A) |			\
 	BIT(POWER_DOMAIN_TRANSCODER_EDP) |		\
+	BIT(POWER_DOMAIN_TRANSCODER_MIPI_A) |		\
+	BIT(POWER_DOMAIN_TRANSCODER_MIPI_C) |		\
 	BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |		\
 	BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |		\
 	BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |		\