From patchwork Tue Oct 27 09:38:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 7495231 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CFBAB9F399 for ; Tue, 27 Oct 2015 09:37:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BEE7720864 for ; Tue, 27 Oct 2015 09:37:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A59B520863 for ; Tue, 27 Oct 2015 09:37:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 87A916EA69; Tue, 27 Oct 2015 02:37:05 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F06C6EA69 for ; Tue, 27 Oct 2015 02:37:02 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP; 27 Oct 2015 02:36:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,204,1444719600"; d="scan'208";a="835967191" Received: from sakamble-desktop.iind.intel.com ([10.223.82.56]) by orsmga002.jf.intel.com with ESMTP; 27 Oct 2015 02:36:55 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Tue, 27 Oct 2015 15:08:54 +0530 Message-Id: <1445938734-1584-1-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 Cc: shashidhar.hiremath@intel.com Subject: [Intel-gfx] [PATCH 1/1] drm/i915/gen9: Check BIOS RC6 setup before enabling RC6 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP RC6 setup is shared between BIOS and Driver. BIOS sets up subset of RC6 configuration registers. If those are not setup Driver should not enable RC6. For implementing this, driver can check RC_CTRL0 and RC_CTRL1 values to know if BIOS has enabled HW/SW RC6. This will also enable user to control RC6 using BIOS settings alone. Change-Id: If89518708e133be6b3c7c6f90869fb66224b7b87 Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/intel_pm.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9dda3ea..8c595e0 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4836,6 +4836,15 @@ static void gen8_enable_rps(struct drm_device *dev) struct intel_engine_cs *ring; uint32_t rc6_mask = 0; int unused; + bool hw_rc6_enabled, sw_rc6_enabled; + + /* Check if BIOS has enabled HW/SW RC6. Only then enable RC6 */ + hw_rc6_enabled = I915_READ(GEN6_RC_CONTROL) & + (GEN6_RC_CTL_RC6_ENABLE | GEN6_RC_CTL_HW_ENABLE); + sw_rc6_enabled = !(I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) + && (I915_READ(GEN6_RC_STATE) & 0x40000); + if (!(hw_rc6_enabled || sw_rc6_enabled)) + i915.enable_rc6 = 0; /* 1a: Software RC state - RC0 */ I915_WRITE(GEN6_RC_STATE, 0);