From patchwork Thu Nov 5 07:43:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Kumar, Shobhit" X-Patchwork-Id: 7558761 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DB494BEEA4 for ; Thu, 5 Nov 2015 07:43:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 048922081F for ; Thu, 5 Nov 2015 07:43:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id EFAD02081D for ; Thu, 5 Nov 2015 07:43:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E0776E351; Wed, 4 Nov 2015 23:43:29 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 76CF96E351 for ; Wed, 4 Nov 2015 23:43:27 -0800 (PST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP; 04 Nov 2015 23:43:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,246,1444719600"; d="scan'208";a="678749851" Received: from skumar40-mobl.iind.intel.com ([10.223.176.10]) by orsmga003.jf.intel.com with ESMTP; 04 Nov 2015 23:43:25 -0800 From: Shobhit Kumar To: intel-gfx@lists.freedesktop.org Date: Thu, 5 Nov 2015 13:13:21 +0530 Message-Id: <1446709401-27668-1-git-send-email-shobhit.kumar@intel.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <5637A90D.9060002@intel.com> References: <5637A90D.9060002@intel.com> MIME-Version: 1.0 Cc: Shobhit Kumar Subject: [Intel-gfx] [v2] drm/i915/skl: While sanitizing cdclock check the SWF18 as well X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP SWF18 is set if the display has been intialized by the pre-os. It also gives what configuration is enabled on which pipe. In skl_sanitize_cdclk, the DPLL sanity check can pass even if GOP/VBIOS is not loaded as BIOS enables DPLL for integrated audio codec related programming. So fisrt check if SWF18 is set and then follow through with other DPLL and CDCLK verification. If not set then for sure we need to sanitize the cdclock. v2: Update the commit message for clarity (Siva) Cc: Ville Syrjälä Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9ee9481..bd476ff 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5006,6 +5006,9 @@ enum skl_disp_power_wells { #define SWF1(i) (dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4) #define SWF3(i) (dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4) +/* VBIOS flag for display initialized status */ +#define GEN6_SWF18 (dev_priv->info.display_mmio_offset + 0x4F060) + /* Pipe B */ #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 103cacb..0ecb35c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5761,6 +5761,14 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) uint32_t cdctl = I915_READ(CDCLK_CTL); int freq = dev_priv->skl_boot_cdclk; + /* + * check if the pre-os intialized the display + * There is SWF18 scratchpad register defined which is set by the + * pre-os which can be used by the OS drivers to check the status + */ + if ((I915_READ(GEN6_SWF18) & 0x00FFFF) == 0) + goto sanitize; + /* Is PLL enabled and locked ? */ if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) goto sanitize;