| Message ID | 1446726932-14078-1-git-send-email-shobhit.kumar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, 05 Nov 2015, Shobhit Kumar <shobhit.kumar@intel.com> wrote: > SWF18 is set if the display has been intialized by the pre-os. It also > gives what configuration is enabled on which pipe. In skl_sanitize_cdclk, > the DPLL sanity check can pass even if GOP/VBIOS is not loaded as BIOS > enables DPLL for integrated audio codec related programming. > So fisrt check if SWF18 is set and then follow through with other DPLL > and CDCLK verification. If not set then for sure we need to sanitize the > cdclock. > > v2: Update the commit message for clarity (Siva) > v3: Correct the mask to check for bits[23:0] instead of only bits[16:0]. > Had missed checking for PIPE C altogether. Remaining are reserved (Siva) > v4: Use ILK_SWF macro for SWF register definitions. Taken from Ville's patch > http://lists.freedesktop.org/archives/intel-gfx/2015-November/079480.html > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> Pushed to drm-intel-next-queued, thanks for the patch and review. BR, Jani. > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ > 2 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9ee9481..e8f1d42 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5005,6 +5005,7 @@ enum skl_disp_power_wells { > #define SWF0(i) (dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4) > #define SWF1(i) (dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4) > #define SWF3(i) (dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4) > +#define SWF_ILK(i) (0x4F000 + (i) * 4) > > /* Pipe B */ > #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 103cacb..512747a 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5761,6 +5761,14 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) > uint32_t cdctl = I915_READ(CDCLK_CTL); > int freq = dev_priv->skl_boot_cdclk; > > + /* > + * check if the pre-os intialized the display > + * There is SWF18 scratchpad register defined which is set by the > + * pre-os which can be used by the OS drivers to check the status > + */ > + if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) > + goto sanitize; > + > /* Is PLL enabled and locked ? */ > if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) > goto sanitize;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9ee9481..e8f1d42 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5005,6 +5005,7 @@ enum skl_disp_power_wells { #define SWF0(i) (dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4) #define SWF1(i) (dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4) #define SWF3(i) (dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4) +#define SWF_ILK(i) (0x4F000 + (i) * 4) /* Pipe B */ #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 103cacb..512747a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5761,6 +5761,14 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) uint32_t cdctl = I915_READ(CDCLK_CTL); int freq = dev_priv->skl_boot_cdclk; + /* + * check if the pre-os intialized the display + * There is SWF18 scratchpad register defined which is set by the + * pre-os which can be used by the OS drivers to check the status + */ + if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) + goto sanitize; + /* Is PLL enabled and locked ? */ if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) goto sanitize;
SWF18 is set if the display has been intialized by the pre-os. It also gives what configuration is enabled on which pipe. In skl_sanitize_cdclk, the DPLL sanity check can pass even if GOP/VBIOS is not loaded as BIOS enables DPLL for integrated audio codec related programming. So fisrt check if SWF18 is set and then follow through with other DPLL and CDCLK verification. If not set then for sure we need to sanitize the cdclock. v2: Update the commit message for clarity (Siva) v3: Correct the mask to check for bits[23:0] instead of only bits[16:0]. Had missed checking for PIPE C altogether. Remaining are reserved (Siva) v4: Use ILK_SWF macro for SWF register definitions. Taken from Ville's patch http://lists.freedesktop.org/archives/intel-gfx/2015-November/079480.html Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ 2 files changed, 9 insertions(+)