From patchwork Wed Nov 25 11:26:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kahola X-Patchwork-Id: 7698091 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 39C85BF90C for ; Wed, 25 Nov 2015 11:26:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6000C20859 for ; Wed, 25 Nov 2015 11:26:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 772BA2083D for ; Wed, 25 Nov 2015 11:26:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F1D0B6EA97; Wed, 25 Nov 2015 03:26:42 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id A71EA6EA97 for ; Wed, 25 Nov 2015 03:26:41 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 25 Nov 2015 03:26:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,342,1444719600"; d="scan'208";a="859432553" Received: from sorvi.fi.intel.com ([10.237.72.63]) by fmsmga002.fm.intel.com with ESMTP; 25 Nov 2015 03:26:40 -0800 From: Mika Kahola To: intel-gfx@lists.freedesktop.org Date: Wed, 25 Nov 2015 13:26:41 +0200 Message-Id: <1448450801-3927-1-git-send-email-mika.kahola@intel.com> X-Mailer: git-send-email 1.9.1 Subject: [Intel-gfx] [PATCH] drm/i915: Disable FLT if DP config changes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Disable DP fast link training if DP link configuration changes. If one of the DP link parameters i.e. link bandwidth, lane count, rate selection, port clock or bpp changes the link training does no longer apply the previously computed voltage swing and pre-emphasis values. Instead, the link training is started with zero values. The patch is fix for reported screen flickering issue in https://bugs.freedesktop.org/show_bug.cgi?id=91393 Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/intel_dp.c | 6 ++++++ drivers/gpu/drm/i915/intel_dp_link_training.c | 27 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 6 +++++- 3 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2805f0d..3694e3f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1621,6 +1621,12 @@ found: intel_dp_compute_rate(intel_dp, pipe_config->port_clock, &link_bw, &rate_select); + intel_dp->link_bw = link_bw; + intel_dp->rate_select = rate_select; + intel_dp->lane_count = lane_count; + intel_dp->port_clock = pipe_config->port_clock; + intel_dp->bpp = bpp; + DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", link_bw, rate_select, pipe_config->lane_count, pipe_config->port_clock, bpp); diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c index 8888793..36a5294 100644 --- a/drivers/gpu/drm/i915/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c @@ -82,9 +82,31 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, } static bool +intel_dp_check_conf(struct intel_dp *intel_dp) +{ + if (intel_dp->link_bw != intel_dp->old_link_bw) + return false; + else if (intel_dp->lane_count != intel_dp->old_lane_count) + return false; + else if (intel_dp->rate_select != intel_dp->old_rate_select) + return false; + else if (intel_dp->port_clock != intel_dp->old_port_clock) + return false; + else if (intel_dp->bpp != intel_dp->old_bpp) + return false; + else + return true; +} + +static bool intel_dp_reset_link_train(struct intel_dp *intel_dp, uint8_t dp_train_pat) { + intel_dp->train_set_valid &= intel_dp_check_conf(intel_dp); + + DRM_DEBUG_KMS("flt enabled: %s\n", + intel_dp->train_set_valid ? "true" : "false"); + if (!intel_dp->train_set_valid) memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); intel_dp_set_signal_levels(intel_dp); @@ -305,6 +327,11 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) if (channel_eq) { intel_dp->train_set_valid = true; + intel_dp->old_link_bw = intel_dp->link_bw; + intel_dp->old_rate_select = intel_dp->rate_select; + intel_dp->old_lane_count = intel_dp->lane_count; + intel_dp->old_port_clock = intel_dp->port_clock; + intel_dp->old_bpp = intel_dp->bpp; DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); } } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 8fae824..8db9288 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -742,7 +742,11 @@ struct intel_dp { i915_reg_t aux_ch_data_reg[5]; uint32_t DP; int link_rate; - uint8_t lane_count; + uint8_t lane_count, old_lane_count; + uint8_t link_bw, old_link_bw; + uint8_t rate_select, old_rate_select; + int port_clock, old_port_clock; + int bpp, old_bpp; bool has_audio; enum hdmi_force_audio force_audio; bool limited_color_range;