From patchwork Wed Dec 2 12:15:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zanoni, Paulo R" X-Patchwork-Id: 7745441 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 806F79F350 for ; Wed, 2 Dec 2015 12:15:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9E1C82063E for ; Wed, 2 Dec 2015 12:15:46 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id B3EB320638 for ; Wed, 2 Dec 2015 12:15:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C826C6E993; Wed, 2 Dec 2015 04:15:44 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id E09A56E98C for ; Wed, 2 Dec 2015 04:15:41 -0800 (PST) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP; 02 Dec 2015 04:15:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,373,1444719600"; d="scan'208";a="6128719" Received: from cmmckee-mobl1.amr.corp.intel.com (HELO panetone.amr.corp.intel.com) ([10.254.186.141]) by fmsmga004.fm.intel.com with ESMTP; 02 Dec 2015 04:15:41 -0800 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Wed, 2 Dec 2015 10:15:23 -0200 Message-Id: <1449058527-13425-8-git-send-email-paulo.r.zanoni@intel.com> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1449058527-13425-1-git-send-email-paulo.r.zanoni@intel.com> References: <1449058527-13425-1-git-send-email-paulo.r.zanoni@intel.com> Subject: [Intel-gfx] [PATCH 07/11] drm/i915: check for FBC planes in the same place as the pipes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This moves the pre-gen4 check from update() to enable(). The HAS_DDI in the original code is not needed since only gen 2/3 have the plane swapping code. v2: Rebase. v3: Extract fbc_on_plane_a_only() (Chris). Reviewed-by: Chris Wilson Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_fbc.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 958f973..8460e3d 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -51,6 +51,11 @@ static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv) return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8; } +static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv) +{ + return INTEL_INFO(dev_priv)->gen < 4; +} + /* * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's @@ -514,6 +519,9 @@ static bool crtc_can_fbc(struct intel_crtc *crtc) if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) return false; + if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) + return false; + return true; } @@ -802,12 +810,6 @@ static void __intel_fbc_update(struct intel_crtc *crtc) goto out_disable; } - if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) && - crtc->plane != PLANE_A) { - set_no_fbc_reason(dev_priv, "FBC unsupported on plane"); - goto out_disable; - } - /* The use of a CPU fence is mandatory in order to detect writes * by the CPU to the scanout and trigger updates to the FBC. */