From patchwork Tue Dec 15 15:28:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Micha=C5=82_Winiarski?= X-Patchwork-Id: 7855171 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B3A4E9F71A for ; Tue, 15 Dec 2015 15:29:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AAEAA203B7 for ; Tue, 15 Dec 2015 15:29:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id BB3FD203DA for ; Tue, 15 Dec 2015 15:29:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0D6A46E730; Tue, 15 Dec 2015 07:29:04 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id B51B76E730 for ; Tue, 15 Dec 2015 07:29:02 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 15 Dec 2015 07:29:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,432,1444719600"; d="scan'208";a="871973232" Received: from irsmsx101.ger.corp.intel.com ([163.33.3.153]) by orsmga002.jf.intel.com with ESMTP; 15 Dec 2015 07:29:01 -0800 Received: from mwiniars-desk1.ger.corp.intel.com (172.28.173.39) by IRSMSX101.ger.corp.intel.com (163.33.3.153) with Microsoft SMTP Server id 14.3.248.2; Tue, 15 Dec 2015 15:29:00 +0000 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: Date: Tue, 15 Dec 2015 16:28:55 +0100 Message-ID: <1450193335-24756-1-git-send-email-michal.winiarski@intel.com> X-Mailer: git-send-email 2.5.0 MIME-Version: 1.0 X-Originating-IP: [172.28.173.39] Cc: =?UTF-8?q?Kristian=20H=C3=B8gsberg=20Kristensen?= Subject: [Intel-gfx] [PATCH libdrm] intel: Restore formatting of offsets in debug statements X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Using lower_32_bits and upper_32_bits macros was accidentally dropped in: commit 8b4d57e7b75cb0bd01d11ad7f597909034a316aa Author: Micha? Winiarski Date: Wed Sep 9 16:07:10 2015 +0200 intel: Add support for softpin Let's restore previous, more readable format. Cc: Kristian Høgsberg Kristensen Signed-off-by: Micha? Winiarski Reviewed-by: Kenneth Graunke --- intel/intel_bufmgr_gem.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 265516f..dc28200 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -438,16 +438,18 @@ drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem) drm_intel_bo_gem *target_gem = (drm_intel_bo_gem *) target_bo; - DBG("%2d: %d %s(%s)@0x%016llx -> " - "%d (%s)@0x%016llx + 0x%08x\n", + DBG("%2d: %d %s(%s)@0x%08x %08x -> " + "%d (%s)@0x%08x %08x + 0x%08x\n", i, bo_gem->gem_handle, bo_gem->is_softpin ? "*" : "", bo_gem->name, - (unsigned long long) bo_gem->relocs[j].offset, + upper_32_bits(bo_gem->relocs[j].offset), + lower_32_bits(bo_gem->relocs[j].offset), target_gem->gem_handle, target_gem->name, - (unsigned long long) target_bo->offset64, + upper_32_bits(target_bo->offset64), + lower_32_bits(target_bo->offset64), bo_gem->relocs[j].delta); } @@ -456,14 +458,15 @@ drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem) drm_intel_bo_gem *target_gem = (drm_intel_bo_gem *) target_bo; DBG("%2d: %d %s(%s) -> " - "%d *(%s)@0x%016lx\n", + "%d *(%s)@0x%08x %08x\n", i, bo_gem->gem_handle, bo_gem->is_softpin ? "*" : "", bo_gem->name, target_gem->gem_handle, target_gem->name, - target_bo->offset64); + upper_32_bits(target_bo->offset64), + lower_32_bits(target_bo->offset64)); } } } @@ -2242,10 +2245,12 @@ drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem) * has relocated our object... Indicating a programming error */ assert(!bo_gem->is_softpin); - DBG("BO %d (%s) migrated: 0x%016llx -> 0x%016llx\n", + DBG("BO %d (%s) migrated: 0x%08x %08x -> 0x%08x %08x\n", bo_gem->gem_handle, bo_gem->name, - (unsigned long long) bo->offset64, - (unsigned long long) bufmgr_gem->exec2_objects[i].offset); + upper_32_bits(bo->offset64), + lower_32_bits(bo->offset64), + upper_32_bits(bufmgr_gem->exec2_objects[i].offset), + lower_32_bits(bufmgr_gem->exec2_objects[i].offset)); bo->offset64 = bufmgr_gem->exec2_objects[i].offset; bo->offset = bufmgr_gem->exec2_objects[i].offset; }