From patchwork Wed Dec 16 18:36:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gordon X-Patchwork-Id: 7865591 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 82B969F6FA for ; Wed, 16 Dec 2015 18:37:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AF7EF203A5 for ; Wed, 16 Dec 2015 18:37:09 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D2EC32021F for ; Wed, 16 Dec 2015 18:37:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2234E6E20A; Wed, 16 Dec 2015 10:37:08 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 68B166E132 for ; Wed, 16 Dec 2015 10:37:06 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 16 Dec 2015 10:37:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,437,1444719600"; d="scan'208";a="862191535" Received: from dsgordon-linux2.isw.intel.com ([10.102.226.88]) by fmsmga001.fm.intel.com with ESMTP; 16 Dec 2015 10:37:03 -0800 From: Dave Gordon To: intel-gfx@lists.freedesktop.org Date: Wed, 16 Dec 2015 18:36:48 +0000 Message-Id: <1450291011-31486-2-git-send-email-david.s.gordon@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1450291011-31486-1-git-send-email-david.s.gordon@intel.com> References: <1450291011-31486-1-git-send-email-david.s.gordon@intel.com> Organization: Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ Subject: [Intel-gfx] [PATCH 1/4] drm/i915: teardown default context in reverse, update comments X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We set up engines in forwards order, so some things (notably the default context) are "owned" by engine 0 (the render engine, aka "RCS"). For symmetry and to make sure such shared objects don't disappear too early, we should generally run teardown loops in the reverse order, so that engine 0 is processed last. This patch changes i915_gem_context_fini() to do that, and clarifies the comments in i915_gem_context_{init,fini}() about the refcounting of the default {struct intel_)context: the refcount is just ONE, no matter how many rings exist or are active, and this refcount is nominally ascribed to the render ring (RCS), which is set up first and now torn down last. Signed-off-by: Dave Gordon Reviewed-by: Nick Hoath --- drivers/gpu/drm/i915/i915_gem_context.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 900ffd0..e143ea5 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -391,7 +391,13 @@ int i915_gem_context_init(struct drm_device *dev) for (i = 0; i < I915_NUM_RINGS; i++) { struct intel_engine_cs *ring = &dev_priv->ring[i]; - /* NB: RCS will hold a ref for all rings */ + /* + * Although each engine has a pointer to the global default + * context, they don't contribute to the refcount on the + * context. We consider that RCS (which is set up first and + * torn down last) holds this reference on behalf of all the + * other engines + */ ring->default_context = ctx; } @@ -431,14 +437,21 @@ void i915_gem_context_fini(struct drm_device *dev) i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state); } - for (i = 0; i < I915_NUM_RINGS; i++) { + for (i = I915_NUM_RINGS; --i >= 0;) { struct intel_engine_cs *ring = &dev_priv->ring[i]; - if (ring->last_context) + if (ring->last_context) { i915_gem_context_unreference(ring->last_context); + ring->last_context = NULL; + } + /* + * These default_context pointers don't contribute to the + * refcount on the context. We consider that RCS holds its + * reference on behalf of all the other engines, so there's + * just a single unreference() call below. + */ ring->default_context = NULL; - ring->last_context = NULL; } i915_gem_context_unreference(dctx);