| Message ID | 1452679593-3922-5-git-send-email-arun.siluvery@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 13/01/2016 10:06, Arun Siluvery wrote: > Required for, > WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt > WaDisableObjectLevelPreemptionForInstancedDraw:bxt > WaDisableObjectLevelPreemtionForInstanceId:bxt > > According to WA database these are only applicable for BXT:A0 but since > A0 and A1 shares the same GT these are extended for A1 as well. > > These are also required for SKL until B0 but not adding them because they > are pre-production steppings. > > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++++++ > 2 files changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 16ef377..eabd2af 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5998,6 +5998,7 @@ enum skl_disp_power_wells { > #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) > #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) > > +#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20EC) The pattern seems to be lc for hex (0x20ec) > #define GEN8_CS_CHICKEN1 _MMIO(0x2580) > > /* GEN7 chicken */ > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 2241a92..7a46cf1 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1132,6 +1132,15 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) > GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); > } > > + /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ > + /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ > + /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ > + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { > + ret = wa_ring_whitelist_reg(ring, GEN9_CS_DEBUG_MODE1); > + if (ret) > + return ret; > + } > + > return 0; > } > >
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 16ef377..eabd2af 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5998,6 +5998,7 @@ enum skl_disp_power_wells { #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) +#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20EC) #define GEN8_CS_CHICKEN1 _MMIO(0x2580) /* GEN7 chicken */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2241a92..7a46cf1 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1132,6 +1132,15 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); } + /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ + /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ + /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ + if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { + ret = wa_ring_whitelist_reg(ring, GEN9_CS_DEBUG_MODE1); + if (ret) + return ret; + } + return 0; }
Required for, WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt WaDisableObjectLevelPreemptionForInstancedDraw:bxt WaDisableObjectLevelPreemtionForInstanceId:bxt According to WA database these are only applicable for BXT:A0 but since A0 and A1 shares the same GT these are extended for A1 as well. These are also required for SKL until B0 but not adding them because they are pre-production steppings. Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++++++ 2 files changed, 10 insertions(+)